Abstract
Electronic industry had required the smaller size and the higher performance of the device. According to Moore’s law, Technology node which also represents minimum feature size have shrank as rate of 0.7 and density of semiconductor have doubled about every two years. However, decreasing of technology node have been confronted with limit to more dense packaging by two-dimensional large-scale integrated circuits (ICs). Therefore, it is essential that developing of packaging techniques from two-dimensional ICs to three-dimensional ICs. The critical essentials of three-dimensional die stacking technology are TSV (through silicon via) and micro-bump. These technologies have contributed to the appearance of HBM (high bandwidth memory). HBM was packet of the memory, which composed of several stacked layers of the memory chips. Each memory chips were vertically connected by TSV and micro-bump. Thus, HBM have lower RC delay and higher performance of data processing than two-dimensional packaged memory. Even though advance of memory packaging have progressed, the lower pitch size and the higher density of memory chips have been requested ceaselessly in electronics packaging industry. Because the requiring of HPC (high performance computing) in the IT industry field such as AI (artificial intelligence), IOT (internet of things) and VR (virtual reality) have maintained. Especially, in order to accomplish vertical fine height between memory chips in the fine pitch packaging of HBM, micro-bump which consists of copper pillar, deposition of nickel diffusion barrier, and tin-silver or tin-silver-copper based cap have been used. TCB (thermal compression bonding) and reflow process (thermal aging) are typical fabrication process of micro-bump in HBM to combine between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degree Celsius. However, there would be issues of reliability of micro-bump in fine-pitch bonding since intermetallic compound (IMC) formed through the reaction between under bump metallurgy and bump cap at smaller area due to lower pitch. For example, during reaction, if atomic flux difference between top and bottom occurred, kirkendall void which provides track of brittle fracture at IMC layer after reflow process could be formed. Moreover, during reflow, if side wetting of tin atoms from solder occurred, solder depletion can be appeared. Solder depletion also cause a serious issue of reliability of micro-bump. In order to remove these problems and make smaller interconnect, bump cap-less interconnect has been considered. Among many ideas related to bump cap-less interconnect, copper-to-copper direct bonding between copper pillar have been considered due to stability for electromigration, low resistivity and not utilizing IMC. However, more heat energy needs to trigger diffusion. [1] In this study, to decrease the challenges of bump bonding process, copper-to-copper direct bonding was conducted below 300℃. For triggering diffusion between copper below 300℃, high entropy single element (HESE) Cu film have been used. HESE Cu film is electrodeposited film which is reinforced self-annealing property. And HESE Cu films have been fabricated by electrochemical process at condition of low temperature and high current density. The self-annealing property of HESE Cu film arose from high defect density and non-equilibrium grain boundaries at the triple junction. The copper-copper bonding experiments were performed using thermal pressing machine. Thermal parameters and pressure parameters were varied to obtain proper bonded samples. The HESE Cu films were characterized by SEM (scanning electron microscope) and EBSD (Electron backscattering diffraction). The microstructure of HESE Cu films were examined by TEM (transmission electron microscopy). Chen, Chih, Doug Yu, and Kuan-Neng Chen. "Vertical interconnects of microbumps in 3D integration." MRS Bulletin40.3 (2015): 257-263.
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