Thermal Compression Bonding Process Development for C2W Stacking in 3D Package

Abstract

With the development of CMOS Si node shrinking from 65 nm to 32 nm, 28 nm to 14nm, the number of I/O of chips increases dramatically and the space of interconnection bumps becomes smaller and smaller. Fine pitch copper bump technology is more and more widely used in advanced flip chip package. When the pitch between bumps is less than 40um, the conventional mass reflow soldering can no longer meet the accuracy requirement of flip chip mounting. In addition, the warpage of ultra-thin die changes obviously during the reflow process in the process of 3D chip stacking. Thermal Compression Bonding (TCB) process can overcome the above two problems very well. TCB technology fixes the chip in the mounting position by bonding head, and heats the chip in place quickly, so that the bump joint can be formed rapidly, which overcomes the problems of chip misplacement & warpage in the mass reflow process. At present, TCB technology has been widely used in 3D chip stacking. At present, the mainstream HBM packaging adopts via middle TSV process. In the chip assembly, the front side of the DRAM wafer is attached with NCF film through the vacuum film laminator, and then the wafer is sent to dicing. Subsequently, the Thermal Compression Bonding (TCB) process is used to sequentially realize the flip-chip assembly between the multilayer DRAM chips and the logic chip. The main processes involved in HBM assembly also include wafer level molding, molding layer backside grinding, RDL and bumping processes on the backside of logic chip after wafer molding, etc. Based on the technical requirement of 3D multi-layer chip stacking, we design the test vehicle with four layers of 60um thickness chip, in which the top die is a single side bumping chip. In addition to the top layer chip, three layers of bottom chips adopt double-side bumping structure with 10um diameter TSV vertical interconnection. In the chip area of 5x5mm, there are 1158 micro-bumps. The minimum pitch between bumps is 40um and the clearance height after stacking is less than 20um. In this study, Non Conductive Film (NCF) is used in TCB process. NCF is a substitute material for traditional liquid Non Conductive Paste (NCP). The same as NCP, NCF is also a kind of thermosetting material. It warps the bump at high temperature and becomes solid when it cools down to room temperature. At the end of the process, NCF fills the gap and protects the bump. There are several technical difficulties in TCB-NCF process development, including NCF film vacuum lamination, multi-layer chip stacking, TCB bonding parameter adjustment and etc. In this study, 100% bump joint interconnection in die stacking is achieved by optimizing TCB parameters. Meanwhile, NCF can fully fill the gap between chips and pass C-SAM inspection. NCF thickness is optimized to ensure the minimum bleeding out. After the bottom chip is bonded to the silicon bare die by TCB-NCF method, the fully oven cure of NCF material is arranged, and then the stacking of the subsequent three chips is completed with the same process flow. TCB-NCF assembly process for C2W (Chip to Wafer) stacking is developed successfully.