Panel-Level Chip-Scale Package With Multiple Diced Wafers

Abstract

In this study, a very high-throughput and low-cost packaging method for fabricating the fan-in chip-scale package is presented. Emphasis is placed on the utilization of the existing printed circuit board (PCB) panel carriers and the corresponding PCB equipment for making the redistribution-layers (RDLs), vias, under bump metallurgy (UBM), contact pads, solder mask, and surface finishing of the package. Since all the PCB panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized.