Bulk Metal-oxide-semiconductor Field-effect Transistors Research Articles

Static power characteristics of selective buried oxide CMOS devices

AbstractSelective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on insulator (SOI) MOSFET devices while maintaining the advantages of bulk MOSFET. In this paper, static power dissipation of SELBOX structure is investigated and compared with SOI and bulk structures. Various MOSFET structures are simulated and evaluated in terms of their static power dissipation. Only results from 90‐nm Complementary Metal Oxide Semiconductor (CMOS) technology devices are included in this paper. Simulation results using the Silvaco TCAD show that static power dissipation in SELBOX CMOS is similar to that of SOI devices but lower than that of bulk CMOS. Hence, SELBOX structure is found to produce relatively low‐static power dissipation while maintaining high operating speed and reducing self‐heating and kink effect. A mathematical model to describe the static power dissipation in the subthreshold region is also included. Statistical analysis show that the model and fabrication simulation results agree with P < .05 and correlation coefficient of 0.95.

Comprehensive analysis of low-frequency noise variability components in bulk and fully depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistor

The low-frequency noise (LFN) variability in bulk and fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistor (MOSFET) with silicon on thin box (SOTB) technology was investigated. LFN typically shows a flicker noise component and a signal Lorentzian component by random telegraph noise (RTN). At a weak inversion state, the random dopant fluctuation (RDF) in a channel is strongly affected to not only RTN variability but also flicker noise variability in the bulk MOSFET compared with SOTB MOSFET because of local carrier number fluctuation in the channel. On the other hand, the typical level of LFN in SOTB MOSFET is slightly larger than that in the bulk MOSFET because of an additional interface on the buried oxide layer. However, considering the tailing characteristics of LFN variability, LFN in SOTB MOSFET can be assumed to be smaller than that in the bulk MOSFET, which enables the low-voltage operation of analog circuits.

Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching

We demonstrate a nearly hysteresis-free sub-60-mV/decade subthreshold swing (SS) operation in a p-type bulk metal–oxide–semiconductor field-effect transistor externally connected to a ferroelectric capacitor. The SS $\mu \text{m}\sim 10$ nA/ $\mu \text{m}$ of drain current) and at large drain current levels. However, the extent of hysteresis is found to be strongly dependent on the drain voltage. At high drain voltages, large hysteresis occurs, indicating the influence of drain voltage in the charge balance with the ferroelectric capacitor.

Structural Dependence of Source-and-Drain Series Resistance on Saturation Drain Current for Sub-20 nm Metal–Oxide–Semiconductor Field-Effect Transistors

The structural dependence of series-resistance effects on the saturation current is investigated in sub-20 nm metal–oxide–semiconductor field-effect transistors (MOSFETs). For planer bulk, silicon-on-insulator (SOI), and multi gate (MG) MOSFETs, the reduction rate of the saturation current is calculated using an analytical current model in high-performance (HP), low-operating-power (LOP), and low-standby-power (LSTP) technologies. In HP technology, the reduction rates are 29.0, 25.3, and 22.1% for bulk, SOI, and MG MOSFETs, respectively. In LOP technology, the reduction rates are 23.8, 21.5, and 20.7% for bulk, SOI, and MG MOSFETs, respectively. In LSTP technology, the reduction rates are about 17% for all devices. In HP technology, the ratio of the series resistance to the channel resistance is the dominant factor for the reduction rate. In LOP technology, the ratio of the over drive voltage to the supply voltage is the dominant factor. In LSTP technology, both the resistance and voltage ratios are the dominant factors.

Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage $(V_{\rm TH})$ Variation in Quasi-Planar Tri-Gate Bulk MOSFETs

To experimentally investigate the impact of double-patterning and double-etching (2P2E) versus single-patterning and single-etching (1P1E) on the line-edge-roughness (LER) as well as on the LER-induced threshold-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) variation in a multigate bulk device, quasi-planar tri-gate (QPT) bulk metal-oxide semiconductor field-effect transistors (MOSFETs) are fabricated by a 28-nm complementary metal-oxide-semiconductor (CMOS) technology. It is experimentally verified that the LER profile obtained through using the 2P2E 193-nm immersion photolithography technique has a relatively longer correlation length (i.e., lower spatial frequency) than that by the 1P1E technique, although they have a comparable root-mean-square deviation and fractal dimension. By using Monte Carlo simulations to analyze the random <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> variations in the QPT bulk MOSFETs, we confirm that the 2P2E-LER-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> variation (versus the 1P1E-LER-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> variation) is suppressed by ~20% in terms of σ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ). However, the total <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> variation in the QPT MOSFETs is slightly improved with the 2P2E technique, because the other variation sources such as random dopant fluctuation and work-function variation have still dominated the total <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> variation. To fully benefit from the 2P2E technique, the other random/intrinsic variations should be better controlled in the QPT CMOS technology.

An analytic drain current model for long-channel undoped gate stack surrounding-gate MOSFETs including interface fixed charges

SUMMARY On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long-channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding-gate (SRG) metal–oxide–semiconductor field-effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat-band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding-gate MOSFETs of the charge-trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.

Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal–Oxide–Semiconductor Field Effect Transistors

The variability of subthreshold swing (SS) in fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) MOSFETs is statistically analyzed and compared with that of conventional bulk MOSFETs. It is newly found that SS variability is small enough in deep subthreshold region (small drain current Ids) while it increases as increasing Ids. The mechanisms of this behavior is intensively investigated and it is found that the increase in SS variability is caused by current-onset voltage (COV) variability that is due to random dopant fluctuation (RDF). Since SOTB FETs have small COV variability thanks to an intrinsic channel, SS variability is much smaller than bulk FETs, which is a great advantage of FD SOTB in terms of Ion/Ioff ratio.

Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs

Quasi-planar tri-gate (QPT) bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated by a low-power 28-nm complementary metal-oxide-semiconductor (CMOS) technology, in order to investigate the effect of double-patterning and double-etching (2P2E) on the line-edge-roughness (LER) as well as on the LER-induced threshold-voltage (VTH) variation. We experimentally verified that the LER profile obtained by the 2P2E 193nm immersion photolithography technique has a relatively lower spatial frequency (i.e., longer correlation length) than that obtained by the conventional (i.e., single-patterning and single-etching, or 1P1E) photolithography technique, although they have a comparable root-mean-square deviation and fractal dimension. Using Monte Carlo (MC) simulations to analyze the random VTH variations in the QPT bulk MOSFETs, we confirmed that the 2P2E-LER-induced VTH variation is much smaller than the total VTH variation in the 28nm QPT CMOS technology.

Electron Mobility Limited by Remote Charge Scattering in Thin (100)- and (110)-Oriented Silicon Body Double-Gated Metal–Oxide–Semiconductor Field-Effect Transistors with High-k Gate Dielectrics

We have investigated the electron mobility limited by the remote charge scattering, µRCS, in the thin silicon body (≤8 nm) double-gated metal–oxide–semiconductor field-effect transistors (MOSFETs), focusing on its dependency on the body thickness and the silicon surface orientation. In order to predict the µRCS in such an unprecedented MOSFET system, the adequacy of physical models used in the computation was verified by comparing the computational results with the experimentally determined µRCS from the actual bulk MOSFETs with high-k dielectric fabricated on the (100) and (110) silicon substrates. It has been discovered for the first time that the µRCS is dropped to less than half of the bulk device's µRCS when the body thickness is 5 nm and that the µRCS lowering derived from the body thickness reduction is more serious in the (110)-oriented surface than in the (100)-oriented surface. These mobility trends have been quantitatively explained by the effective mass difference between the two surfaces as well as by the carrier confinement in the metallurgically defined narrow silicon body. These observations indicate the great importance of the systematic reduction of charged traps in high-k gate dielectrics in the advanced devices.

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

This paper presents the statistical analysis of a newly found drain current variability component called “current-onset voltage” (COV) variability as well as drain induced barrier lowering (DIBL) variability in bulk and fully-depleted (FD) silicon-on-insulator (SOI) devices. Intensive variability measurement data show that gate length and gate width dependent COV variability and DIBL variability in bulk metal–oxide–semiconductor field effect transistors (MOSFETs) deviate from the straight line in the Pelgrom plot. On the other hand, COV variability and DIBL variability in FD SOI MOSFETs fall on the straight line. Their mechanisms are discussed based on three-dimensional (3D) device simulation considering random dopant fluctuation (RDF). It is found that the saturation of the COV and DIBL variability in smaller devices is caused by weaker averaging effect of channel potentials.

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

This paper presents the statistical analysis of a newly found drain current variability component called “current-onset voltage” (COV) variability as well as drain induced barrier lowering (DIBL) variability in bulk and fully-depleted (FD) silicon-on-insulator (SOI) devices. Intensive variability measurement data show that gate length and gate width dependent COV variability and DIBL variability in bulk metal–oxide–semiconductor field effect transistors (MOSFETs) deviate from the straight line in the Pelgrom plot. On the other hand, COV variability and DIBL variability in FD SOI MOSFETs fall on the straight line. Their mechanisms are discussed based on three-dimensional (3D) device simulation considering random dopant fluctuation (RDF). It is found that the saturation of the COV and DIBL variability in smaller devices is caused by weaker averaging effect of channel potentials.

Accurate Extraction and Modeling of High-Temperature-Dependent Channel Mobility in Metal–Oxide–Semiconductor Field-Effect Transistors Using Measured S-Parameters

An improved RF method based on the slope extraction of the total drain–source resistance and total gate charge versus mask gate length from measured S-parameters is presented to extract the effective channel mobility of bulk metal–oxide–semiconductor field-effect transistors (MOSFETs) from 27 to 250 °C. An improved temperature-dependent channel mobility equation is also used to eliminate the high-temperature modeling errors in the conventional equation. Much better agreement with measured electron mobility data from 27 to 250 °C is achieved by using the improved equation rather than the conventional one, verifying the accuracy of the improved equation.

Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants

Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.

Silicon thickness fluctuation scattering dependence of electron mobility in ultrathin body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors

A matrix element for thickness fluctuation (δTSOI) scattering was derived to demonstrate the mobility dependence on Eeff, especially at a low inversion charge concentration, with an ultrathin channel thickness below 7 nm. This case contrasts other research with a lack of such dependence on either thick silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) or bulk MOSFETs. Our matrix element implies that the quantized energy fluctuation associated with δTSOI varies with the average distance of electrons from the surface interface. In particular, it implies the effects of the change in transverse potential on the subband energy fluctuation for each subband, which results in a different matrix element for each applied gate bias. By using this matrix element model, the low-field electron mobility was shown to depend not only on TSi but also on Eeff. Furthermore, the results of a simulation of electron mobility degradation as a function of TSi at low Eeff agreed well with previous experimental results.

Experimental Study of Effective Carrier Mobility of Multi-Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with (111) Channel Surface Fabricated by Orientation-Dependent Wet Etching

We present an experimental study of effective carrier mobility ( µeff) of multi-fin-type double-gate metal–oxide–semiconductor field-effect transistors (FinFETs) with a (111) channel surface fabricated by orientation-dependent wet etching. The peak values of the obtained µeff of electrons and holes are approximately 300 and 160 cm2/(V s), respectively, which are close to those in (111) bulk metal–oxide–semiconductor field-effect transistors (MOSFETs). Moreover, the effective electric field (Eeff) dependence of the µeff of electrons and holes shows a good agreement with the mobility universal curves of (111) bulk MOSFETs. These results indicate that the quality and channel surface roughness of Si-fins by orientation-dependent wet etching are excellent. The obtained results of µeff are very useful for the modeling and design of FinFET-complementary metal–oxide–semiconductor (CMOS) circuits and the developed wet etching technique is very attractive in the fabrication of ultrathin and high-quality Si-fin channels.

Temperature Dependence of Off-Current in Bulk and Fully Depleted SOI MOSFETs

Re-examinations of the temperature dependence of off-current (Ioff) in metal oxide semiconductor field-effect transistors (MOSFETs) have been carried out, from 0.25 µm to 65 nm technology nodes comparing bulk MOSFETs to fully depleted silicon on insulator (FD SOI) MOSFETs. Analytical calculations and two-dimensional (2D) device simulations are performed, and the ratio of Ioff at a high temperature to that at room temperature has been focused on for discussion. The temperature dependence of Ioff consists of two components: subthreshold factor component (S component) and threshold voltage component (Vth component). It is found that the Vth component determines the relative merits of bulk and FD SOI MOSFETs, and originates from the difference in the temperature dependence of Vth. It is also found from the simulation that, although the advantage of FD SOI MOSFETs remains when the short-channel effect can be neglected, it diminishes when the short-channel effect is dominant as the technology node advances.

In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore's law, new materials and structures are required. The first major material change to extend Moore's law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si channel for 20%-50% mobility enhancement. For the next several logic technologies, MOSFETs will improve though higher levels of uniaxial process stress. After that, new materials that address MOSFET poly-Si gate depletion, gate thickness scaling, and alternate device structures (FinFET, tri-gate, or carbon nanotube) are possible technology directions. Which of these options are implemented depends on the magnitude of the performance benefit versus manufacturing complexity and cost. Finally, for future material changes targeted toward enhanced transistor performance, there are three key points: 1) performance enhancement options need to be scalable to future technology nodes; 2) new transistor features or structures that are not additive with current enhancement concepts may not be viable; and 3) improving external resistance appears more important than new channel materials (like carbon nanotubes) since the ratio of external to channel resistance is approaching /spl sim/1 in nanoscale planar MOSFETs.

Breakdown Voltage in Uniaxially Strained n-Channel SOI MOSFET

The drain breakdown voltage of n-channel silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFETs) was found to decrease with the application of uniaxial tensile strain along the channel. The decrease in drain breakdown voltage was found to depend on the direction of the strain applied with respect to the current flow. To investigate the mechanism of this phenomenon, the influence of uniaxial tensile strain on built-in potential at the source junction and on impact ionization was investigated using an SOI lateral diode and bulk MOSFET. Uniaxial strain was induced by mechanically applying bending deformation to the chip using a cantilever structure. Built-in potential at the source junction remained unchanged. Impact ionization rate at the drain edge of MOSFET was found to increase with increasing uniaxial tensile strain. This increase in impact ionization rate is shown to be the cause of the reduced drain breakdown of SOI MOSFET in the presence of uniaxial strain.

Improvement of Surface Morphology of Epitaxial Silicon Film for Elevated Source/Drain Ultrathin Silicon-on-Insulator Complementary-Metal-Oxide-Semiconductor Devices

A novel selective epitaxial growth (SEG) technology which uses ultrahigh-vacuum chemical vapor deposition and low-damage sidewall etching with a Cl2-plasma gas is experimentally demonstrated for elevated source/drain (S/D) ultrathin silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) devices. It is found that the deviation of parasitic S/D series resistance in elevated S/D sub-40-nm-thick SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) can be nearly as low as that in bulk MOSFETs, because the excellent surface morphology of the epitaxial Si layer enables formation of a uniform CoSi2 film. Moreover, neither gate/drain bridging nor any other leakage phenomena are pronounced. These results indicate that this SEG technology is promising for elevated S/D ultrathin SOI CMOS devices for the 90-nm technology node and beyond.

Quantum-Mechanical Simulation of Gate Tunneling Current in Accumulated n-Channel Metal-Oxide-Semiconductor Devices with n+-Polysilicon Gates

The gate tunneling current in n+-polysilicon gate n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in accumulation regime has been simulated quantum-mechanically. The two current components, due to hole tunneling from the accumulation layer on the p-silicon surface and due to electron tunneling from the accumulation layer on the n+-polysilicon gate, have been investigated for bulk and silicon-on-insulator (SOI) MOSFETs with various SOI layer thicknesses. For bulk MOSFETs, the electron current from the gate becomes much larger than the hole current from the silicon surface. On the other hand, as the SOI layer thickness (tSOI) decreases, the hole current increases, but the electron current decreases, and thus the hole current exceeds the electron current at a certain tSOI. The total gate current increases with decreasing tSOI (>2 nm). For extremely thin tSOI, the contribution of the electron current almost disappears. Moreover, the quantum-mechanical effects on the tunneling current in accumulated SOI MOSFETs have been discussed in detail.