Improvement of Surface Morphology of Epitaxial Silicon Film for Elevated Source/Drain Ultrathin Silicon-on-Insulator Complementary-Metal-Oxide-Semiconductor Devices

Abstract

A novel selective epitaxial growth (SEG) technology which uses ultrahigh-vacuum chemical vapor deposition and low-damage sidewall etching with a Cl2-plasma gas is experimentally demonstrated for elevated source/drain (S/D) ultrathin silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) devices. It is found that the deviation of parasitic S/D series resistance in elevated S/D sub-40-nm-thick SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) can be nearly as low as that in bulk MOSFETs, because the excellent surface morphology of the epitaxial Si layer enables formation of a uniform CoSi2 film. Moreover, neither gate/drain bridging nor any other leakage phenomena are pronounced. These results indicate that this SEG technology is promising for elevated S/D ultrathin SOI CMOS devices for the 90-nm technology node and beyond.