Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs

Abstract

Quasi-planar tri-gate (QPT) bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated by a low-power 28-nm complementary metal-oxide-semiconductor (CMOS) technology, in order to investigate the effect of double-patterning and double-etching (2P2E) on the line-edge-roughness (LER) as well as on the LER-induced threshold-voltage (VTH) variation. We experimentally verified that the LER profile obtained by the 2P2E 193nm immersion photolithography technique has a relatively lower spatial frequency (i.e., longer correlation length) than that obtained by the conventional (i.e., single-patterning and single-etching, or 1P1E) photolithography technique, although they have a comparable root-mean-square deviation and fractal dimension. Using Monte Carlo (MC) simulations to analyze the random VTH variations in the QPT bulk MOSFETs, we confirmed that the 2P2E-LER-induced VTH variation is much smaller than the total VTH variation in the 28nm QPT CMOS technology.