Bulk FinFET Research Articles

Temperature-dependent short-channel parameters of FinFETs

The remarkable development and continual proliferation of research in the nanotechnology field have led to improvement in the efficiency of elementary devices. To improve their performance, the parameters of such devices can be scaled down while optimizing their characteristics. However, this simultaneously results in degraded switching characteristics and the appearance of short-channel effects. Multigate-based fin-shaped field-effect transistors (FinFETs) represent a new option to address all these problems. However, thermal failure of FinFET devices under nominal operating conditions is an important issue in the design and implementation of high-speed semiconductor devices. It is also seen that bulk FinFETs exhibit better thermal performance compared with silicon-on-insulator FinFETs. In the work presented herein, various FinFET characteristics including the subthreshold swing, drain-induced barrier lowering, threshold voltage, and drain current were investigated as functions of temperature. The (effective) channel length is larger than the physical gate length (in off-state) due to the undoped underlap regions. This paper also discusses the effects of drain, source, and gate overlap.

Factor Analysis of Plasma-Induced Damage in Bulk FinFET Technology

In this letter, factor analysis is employed to investigate the hidden dependencies and correlations of plasma-induced damage with other FEOL and BEOL parameters in bulk FinFET technology. First, the test structures are described and the amount of threshold voltage shift resulting from plasma damage is characterized. Next, the different parameters considered are listed and extracted. Finally, they are correlated to the amount of damage inflicted to the transistors using statistical reduction and factor analysis. It is found that the communality of the shift with the parameters considered may partly explain the degraded variability of plasma damaged MOSFET devices.

Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications

The Fin shaped Field Effect Transistors (FinFETs), are the front runner of the current sub-nanometer technology node. The semiconductor industry adopts it in high-performance (HP) and low-power (LP) applications due to greater electrostatic control and better scalability. This paper explores the numerically simulation based comparison of bulk and silicon-on-insulator (SOI) technology double gate (DG), triple gate (TG) FinFETs. The essential processing steps required to create the GS high-k dielectric bulk and SOI FinFETs are demonstrated. The electrical performance parameters of the device such as Ion/Ioff ratio, subthreshold swing (SS), and drain induced barrier lowering (DIBL) are extracted. Based on the three-dimensional (3D) ATLASTM simulation results, TG FinFET shows an ameliorated performance over DG in bulk and SOI technology as well. In order to control the short channel effects (SCEs), gate-stack (GS) high-k dielectrics are introduced with fixed thickness interfacial-layer (IL) and high-k dielectric material in between the gate material and semiconductor. The GS high-k dielectrics suppress the SCEs to large extent in both devices and technologies. The GS SOI FinFETs demonstrates the improved performance over the bulk counterpart and TG FinFET is the best among them. Further, the similar kind of investigation has been carried out for Tfin variations. These devices reveal the excellent control of SCEs when the fin is narrow. The ratio of SOI and bulk TG FinFET Ion/Ioff ratio with Tfin variations provide evidence that, the SOI based devices are competent for HP and LP applications.

Self-Heating Assessment on Bulk FinFET Devices Through Characterization and Predictive Simulation

This paper describes three different measurement methodologies for the electrical characterization of FinFET self-heating at wafer-level. Finite element simulations of heat transport are used to interpret heater-sensor temperature gradients and validate the measurements. The different sensor types were designed to use the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of an adjacent FET, the forward bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) of an adjacent pn-junction or the gate resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) of the device itself. We report that self-heating is underestimated by 35% when sensed at a neighboring device. We also confirm that heat from local and surrounding sources are additive.

Modeling of Advanced RF Bulk FinFETs

The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.

Impact of Local-Interconnect to Gate Overlay on Series Resistance Compensation for Injection Velocity Extraction

The extraction of the injection velocity in CMOS requires compensation of the transistor series resistances. They are usually evaluated in the linear regime, assuming that the source and drain terminals contribute equally to it. Due to the overlay between gate and local interconnect, this is however not the case. This paper investigates the consequences on the injection velocity extraction procedure, and proposes a new approach to compensate for the asymmetry of the device. The difference between the saturation transconductances obtained by swapping the MOSFET junction terminals is used to extract the source resistance, and thus enables accurate resistance compensation of the inversion charge and current in the saturation regime. This method is tested on a bulk FinFET technology to demonstrate its validity, and the results are correlated with metrology measurements.

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is −11.7 dBm OMA at a bit error rate of 10−12 with PRBS31 data, providing 12.9-dB link margin.

Ge-cap quantum-well bulk FinFET for 5 nm node CMOS integration

We propose the use of Ge-cap quantum-well (QW) bulk FinFET for 5 nm CMOS integration, which is a Si channel wrapped with Ge around three sides of the fin channel. The simulation results show that the Ge-cap FinFET structure demonstrates better performance than pure Si, pure Ge, and Si-cap FinFET structures. By optimizing Si fin width and Ge-cap thickness, the on-state current of nFET and pFET can also be symmetric without changing the total fin width (FWp = FWn). The electrons in Ge-cap nFinFET concentrate in the Si channel because of QWs formed in the lowest conduction band of the Ge and Si heterostructure, while the holes in Ge-cap pFinFET prefer to stay in Ge surfaces owing to QWs formed in the Ge valence band. The physics studies of this device have made the design rules relevant for the application of the CMOS inverter and static random access memory (SRAM) application technology.

Analysis of In-Line Process Parameters of the Unity Gain Frequency of HKMG Bulk FinFET Devices

This research explores the electrical characteristics of the unity gain frequency ( ${F}_{t}$ ) in relation to the experimental in-line process parameters of 16-nm high- $\kappa $ metal gate bulk fin-type field effect transistor devices. Because ${F}_{t}$ is dependent on the transconductance ( ${G}_{m}$ ) and effective gate capacitance ( ${C}_{\textsf {gg}}$ ), a sensitivity analysis of these two factors is applied to determine key in-line process parameters. The engineering results of this letter indicate that ${G}_{m}$ and ${C}_{\textsf {gg}}$ are significantly fluctuated by six in-line process parameters, including the gate length, fin height, high- $\kappa $ /interfacial layer thickness, source/drain (S/D) proximity, S/D depth, and gate height. These six parameters fluctuate ${F}_{t}$ at the same time, with ${G}_{m}$ as the dominant factor.

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

This paper describes the design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity. Charge trap transistors (CTTs) that exploit charge trapping and de-trapping behavior in high-K dielectric of 32-/22-nm Logic FETs are used as storage elements with logic-compatible programming voltages. A high-gain slew-sense amplifier (SA) is used to efficiently detect the threshold voltage difference ( $\Delta V_{\textrm {DIF}}$ ) between the true and complement FETs in the twin cell. Design-assist techniques including multi-step programming with over-write protection and block write algorithm are used to enhance the programming efficiency without causing a dielectric breakdown. High-temperature stress results show a projected data retention of 10 years at 125 °C with a signal loss of <30% that is margined in while programming, by employing a sense margining logic in the SA. Scalability of CTT has been established by the first demonstration of CTT-based MTPM in 14-nm bulk FinFET technology with read cycle time of 40 ns at 0.7-V VDD.

Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs

The non-planar 3D structure of multi-gate FinFETs makes them able to be scaled down to 20 nm and beyond and also have greater performance. But any variation of the fin cross-sectional shape has an impact on the device performance. In this paper, the impact of various fin cross-sectional shape on junctionless accumulation mode bulk FinFETs with thin fins and short channel length has been evaluated. Different important device performance parameters such as ON-current (ION), OFF current (IOFF), ratio of ON/OFF current, Threshold voltage (Vth), Subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (gm/Ids), cut-off frequency (fT), and maximum oscillation frequency (fmax) is evaluated for different fin shapes and analyzed. From the analysis, it is understood that shape of the fin cross-section has substantial impact on performance of the device. Improvement in SCEs was noticed in terms of ~ 25% reduction of DIBL and ~ 10% reduction in SS for the device with reduced fin top width. On the other hand, reduced fin top width degrades the RF performance as maximum frequency of oscillation decrease by ~ 10%. An optimal fin structure for the junctionless bulk FinFET is also obtained to have better SCEs and reasonable Analog/RF applications.

A Study of High-Low Frequency Charge Pumping Method on Evaluating Interface Traps in Bulk FinFETs

Charge pumping (CP) technology is a useful tool to measure interface traps in devices such as planar MOSFETs and SOI FinFETs but scarcely used in bulk FinFETs. In this paper, high-low frequency (HLF) CP was employed to test the interface traps in bulk FinFETs for the first time. Bulk FinFETs fabricated with different process parameters, such as interface areas, post deposition annealing (PDA) temperatures, interface layer (IL) deposition and high-κ(HK) layer deposition conditions, were charcaterized systematically. It is followed by the evaluation of gate leakage and breakdown voltage to demonstrate the validity of HLF CP test. Achieved results indicate that HLF CP is an accurate method to evaluate interface traps in bulk FinFETs. It is also found that the gate leakage is affected by the high frequency in tests. And frequencies higher than 2MHz in tests can lead to inaccurate results in as-fabricated bulk FinFETs.

Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs

FinFETs and ultrathin body and buried oxide fully depleted silicon on insulator (UTBB-FDSOI) are the main transistors currently used in advanced integrated circuits (ICs). The tunable electrical properties via back-biasing facilitate the threshold voltage adjustment and enable IC designers to achieve a highly efficient and low-power-consuming operation. This study compares the modulation rate before and after hot carrier stress (HCS) of bulk FinFETs, UTBB-FDSOI ( t BOX = 20 nm), and SOI FinFETs ( t BOX>150 nm) via back-biasing. Simplified back-impedance models are proposed based on the impact of back-biasing on electrical characterization. Additionally, HCS with back-biasing shows a higher impact on UTBB FDSOI than on bulk FinFETs during reliability test, implying that the t BOX plays a critical role in the modulation rate. The lifetime with HCS indicates that the bulk FinFETs exhibit faster downscaling degradation than UTBB FDSOI probably due to the nature of multigate devices whose vertical electrical field should increase faster than planer devices during scaling.

Comparison of bulk FinFET and SOI FinFET

In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software. By changing the parameters of the gate voltage, drain voltage and gate length to analysis which characteristic is better. Through the experiment results, we demonstrate that the SOI FinFET have the better characteristics than bulk FinFET[1].

Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked 6T-SRAM Layout

In this paper, we investigated the source/drain recessed contact structure to mitigate the self-heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of nanowire regions during device operation was considerably decreased by using the source/drain recessed contact structure. This is attributed to an increase in heat dissipation mainly from heat source to bulk wafer. Moreover, we proposed the p/n-stacked nanowire on bulk FinFET and its 6T-SRAM layout. Area of the proposed SRAM was reduced approximately 15%, as compared to the conventional cell layout.

Importance of $\Delta V_{{\text {DIBLSS}}}/({I}_{{\text {on}}} /{I}_{{\text {off}}})$ in Evaluating the Performance of n-Channel Bulk FinFET Devices

This paper aims to investigate the recently proposed figure of merit, $\Delta V_{\mathrm{ DIBLSS}} /(I_{\mathrm{ on}} /I_{\mathrm{ off}})$ , in detail. Experimental results show that $\Delta V_{\mathrm{ DIBLSS}} /(I_{\mathrm{ on}} /I_{\mathrm{ off}})$ represents the index of device immunity to short-channel effects in bulk FinFETs. The value of its numerator, $\Delta V_{\mathrm{ DIBLSS}}$ , accounts for the drain-induced barrier lowering and subthreshold swing. The value of its denominator, $I_{\mathrm{ on}} /I_{\mathrm{ off}}$ , accounts for the transistor performance in transitioning between on and off states. Small $\Delta V_{\mathrm{ DIBLSS}}$ and large $I_{\mathrm{ on}} /I_{\mathrm{ off}}$ are desirable, representing the improved gate control over the channel potential. We found that both $\Delta V_{\mathrm{ DIBL}}$ and $\Delta V_{\mathrm{ SS}}$ values are more correlated with the drain off-state current, $I_{\mathrm{ off}}$ , than they are with the drain on-state current, $I_{\mathrm{ on}}$ . A high-performance FinFET device exhibits $\Delta V_{\mathrm{ DIBLSS}}$ of about 100 mV and $I_{\mathrm{ on}}/I_{\mathrm{ off}}$ of about ${\mathrm{ 1}}\times {\mathrm{ 10}}^{\mathrm{ 6}}$ . Thus, $\Delta V_{\mathrm{ DIBLSS}} /(I_{\mathrm{ on}} /I_{\mathrm{ off}})$ in a high-performance FinFET device is expected to be around ${\mathrm{ 1}}\times {\mathrm{ 10}}^{-{\mathrm{ 4}}}$ mV. Using this figure of merit, along with the verification using conventional parameters such as $\Delta V_{\mathrm{ DIBLSS}}$ and $I_{\mathrm{ on}} /I_{\mathrm{ off}}$ , the proposed device shows better electrical characteristics than that in our previous work due to the optimized process conditions implemented.

Exploiting Parallelism and Heterogeneity in a Radiation Effects Test Vehicle for Efficient Single-Event Characterization of Nanoscale Circuits

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency.

The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region.

Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology

Integrated circuits fabricated at advanced technology nodes are expected to operate in gigahertz range of frequencies. At these frequencies, single-event transient (SET)-induced errors result in significant increases in single-event (SE) cross section for flip-flop (FF) designs. For FinFET transistors, the physical structure has changed significantly from planar structure. These changes have resulted in significantly less collected charge than that for planar technologies for the same ion strike, leading to shorter SET pulse generation. These results have necessitated the evaluation of SE cross section for FF designs as a function of frequency for accurate SE predictive capability. Circuit-level simulations and heavy-ion experiments were carried out to investigate frequency dependence of SE cross section for a hardened dual-interlocked cell-based FF design with different spacing options in a 16-nm bulk FinFET technology.

Punch-Through Stop Doping Profile Control via Interstitial Trapping by Oxygen-Insertion Silicon Channel

Interstitial trapping by oxygen-inserted silicon channel results in blocking of boron and phosphorus transient enhanced diffusion as well as retention of channel boron profiles during the gate oxidation process. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28nm planar CMOS and 20nm bulk FinFET devices projected by TCAD have been discussed.