Built-in Self-test Circuit Research Articles

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test

—The built-in self-test (BIST) circuit is designed to be highly integrated with ADC under test and tests the static linearity based on the stimulus error identification and removal (SEIR) method. A novel level shift generator is proposed for high-precision ADC testing to break the resolution limitation caused by thermal noise and non-linearity. The double sampling operation realized by the chopper circuits cancels the sampling kT/C noise, and the circuit further reduces the amplifier's thermal noise by reducing the noise bandwidth. Besides, this paper presents a new method to achieve a highly linearity-constant voltage shift by applying the negative-C technique. Implemented in 180 nm CMOS process, the simulation results show that the noise power of the voltage shift is reduced by 10 dB, and the constancy of voltage shift is only 3.7 ppm over the entire ADC input range. Benefitting from the noise and linearity performance enhancement, this BIST circuit can test 18-bit ADC to 18-bit accuracy level with one-tenth sampling points.

An all-digital built-in-self-test scheme for duty cycle corrector with de-skew circuit in NAND Flash memory

This paper presents an all-digital built-in-self-test (BIST) scheme to quickly test the duty cycle corrector (DCC) with de-skew circuit in NAND Flash memory. The proposed BIST circuit adopts an adjustable duty cycle module to generate the input signal of DCC, then it utilizes a high-resolution vernier time-to-digital converter to quantify the pulse widths related to duty cycle and phase difference into digital codes. The proposed BIST scheme can quickly obtain accurate measurement results of the input/output duty cycle of DCC and the phase difference of signals without using high-precision test equipment, it is a low-cost built-in testing solution for NAND Flash memory. The test chip is fabricated using 130 nm CMOS process. The area occupies 0.0425 mm2, and the proposed circuit consumes 2 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. The experimental results show that the measurement error of duty cycle is in the range of −0.85% to 1.5% and the measurement error of phase difference is within ±6 ps.

Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test

There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, as one of the alternatives in the next generation of semiconductor storage devices. D-flip-flops (DFFs) based on the traditional CMOS process have some shortcomings, including a large area, high power, and charge leakage when scaling down. However, memristors offer a new approach to the design of DFFs with improved performance. Two simplified edge-triggered DFFs are proposed to reduce the number of devices via the Memristor-Rationed Logic (MRL) method, which utilizes the characteristic of transmitting signals in the two-stage inversion structure. In addition, two new 4-bit Linear Feedback Shift Registers (LFSRs) are designed and verified using the proposed DFFs. Compared to the partially existing LFSRs, the designed LFSRs reduce the number of devices significantly, decrease the power consumption by 32.7% and 33.3% and shorten the delay time by 34.5% and 30.7% for the NOR and NAND gates, respectively. Finally, the proposed falling-edge-triggered DFF is used to implement the major blocks of the Built-In Self-Test(BIST) circuit, and the simulation results confirm their correctness and feasibility.

Automatic generation of user-defined test algorithm description file for memory BIST implementation

Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms.

A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology

In this article, a CMOS <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ku</i> -band phased-array transmitter with eight elements is demonstrated. To mitigate the measurement time and complexity, a built-in self-test (BIST) circuit is developed in this chip. A fully symmetrical sampling structure is proposed to improve the testing accuracy of the BIST system. To decrease the phase and amplitude errors, two compensation methods based on inductors and capacitors are, respectively, used in the phase shifters and attenuators to minimize severe parasitic effects of transistors in high-frequency bands. In addition, a scalable power divider is developed to save chip area and reduce insertion loss. According to the measurement results, the 5-bit passive phase shifter in each transmitting channel achieves less than 3.6° root-mean-square phase error (RMSPE) and 0.8-dB root-mean-square amplitude error (RMSAE). The transmitter’s attenuators are formed by four bridge- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T/\pi $ </tex-math></inline-formula> -type units and achieve less than 0.94-dB RMSAE and RMSPE of 3.2°. Each channel of the transmitter is capable of delivering about 13-dBm linear power at 16 GHz. The BIST system is also employed to detect the phase and amplitude performances of the eight-element transmitter, and the BIST testing errors are less than 10.3% compared to the microwave equipment measurement.

Power consumption reduction in built-in self-test circuits

Power consumption reduction in built-in self-test circuits

Design, Implementation and Performance Analysis of Test Pattern Generator for Built-In Self-Test using m-GDI Technology

Background: A Linear Feedback Shift Register (LFSR) is typically used for generating the test patterns in built-in self-test (BIST) as it produces pseudorandom patterns at every clock cycle. These pseudo-random patterns are used as test vectors for testing the VLSI circuits. Objective: The pseudorandom patterns generated by the LFSR exhibit low-correlation among the patterns, this increases the switching activity and power dissipation while testing the VLSI circuit. Thus, to reduce the testing power, modified gate diffusion input (m-GDI) logic based LFSR in 45nm technology is proposed in this paper. Methods: The circuits are developed on m-GDI technology using the Cadence virtuoso tool and a spectre simulator is used to carry out the simulation. Findings: Comparative analysis revealed that the delay and power are reduced significantly, for the proposed design when compared to the existing LFSRs in conventional CMOS, GDI and reversible logic. Novelty and applications: In conventional LFSR, an external source is necessary to load the seed value and it dissipates more power. But in the proposed design, the seed value is generated by the circuit itself. This reduces the power and critical path delay. Further a complete zero patterns is not possible in conventional LFSR design. But in proposed design, all zero pattern is plausible. The design obtained from this study can be applied in low-power, high-speed BIST circuits. Keywords: LFSR; Seed Value; Test Patterns; Built-In-Self-Test; m-GDI

A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge–Response pair acquisition using Built-In Self-Test before shipping

We implemented pseudo-linear feedback shift-register-based physical unclonable functions (PL-PUFs) on silicon and analyzed their performances in terms of reproducibility, uniqueness, and resistance to machine-learning attacks. A PL-PUF is compact and high-throughput PUF, slightly oversensitive to voltage fluctuations. To overcome this drawback, we developed a capturing signal generation circuit that was tolerant to the reproducibility degradation caused by supply voltage changes. We also implemented a Built-In Self-Test (BIST) circuit with an irreversible destruction mechanism to enable exceedingly fast challenge–response pairs (CPRs) for the PUFs before shipping. After the CPRs were evaluated, the BIST circuit became invulnerable to exploitation by attackers.

Synthesis of Built-in Self-Test Control Circuits Based on the Method of Boolean Complement to Constant-Weight 1-out-of-n Codes

We consider the problem of designing a built-in control circuit with full self-testability of control equipment based on the method of Boolean complement to constant-weight 1-out-of-n codes. A method is proposed for determining complementary functions considering the formation of the necessary set of test combinations for a complete check of each element of modulo-2 addition in the structure of the Boolean complement block. Due to the introduction of uncertainties in the selection of values, it is possible to minimize the complexity of control functions, which makes it possible to simplify the control logic block. An algorithm for the synthesis of a built-in self-test control circuit based on the method of Boolean complement to a preselected constant-weight 1-out-of-n code is given.

High-gain inductorless Wideband Balun-LNA using asymmetric CCC & BIST using RMS detectors

In this paper, an inductorless wideband balun-low noise amplifier (LNA) using current source loads, common-mode feedback (CMFB), asymmetric capacitive cross-coupling (CCC) and auxiliary common-source amplifier are proposed to obtain low noise figure (NF) and high gain. The asymmetric CCC boosts the gain and reduces the NF. The CMFB fixes the output to a common mode voltage. RMS detectors are proposed to realize a low-cost built-in self-test (BIST) circuit for measuring the gain of the LNA during its entire lifespan. The proposed balun-LNA is implemented in 0.18 µm CMOS process technology and the performance is studied through post-layout simulations. PVT and Monte Carlo simulations are performed to check for the robustness and yield of the circuit. From these analyses, it is found that the integrated average gain of the LNA obtained with and without the RMS detectors is 19.1 dB and 20.1 dB respectively in the 3 dB-band of 0.18–2 GHz. NF of the LNA in this band is 2.87 dB. The average IIP3, IIP2, and 1 dB compression points of the LNA are (−4.89 dBm, +28.57 dBm, −20.42 dBm) respectively. The proposed LNA dissipates a power of 4.9 mW with a supply of 1.2 V and requires an area of 0.04 mm2.

Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators

Transient performance is one of the most crucial design properties in digital low-dropout regulator (DLDO) design. In this paper, an improved droop measurement built-in self-test (BIST) circuit for DLDOs is presented, expanding on the previous work (Dirican et al. 2018) by the same authors. The proposed BIST system can detect and store the transient droop information using droop detector and generates a digital output with a reuse based 10-bit successive-approximation (SAR) analog-to-digital converter (ADC) with better accuracy. The improvements are achieved by employing a multi-step ramp circuit and a leakage cancellation circuit. The system is made more suitable for process scaling by replacing the analog buffer with a multi-step ramp circuit. Employing a leakage cancellation circuit solves potential leakage problems during ADC operation due to the reused decoupling capacitor of the DLDO and nearly 75% reduction in maximum measurement error is observed using this feature. Additionally, the droop detector is capable of storing transient droop information with less than 0.6% error for droop voltages ranging from 45 mV to 406 mV for a nominal DLDO output voltage of 1.6 V where the supply voltage is 1.8 V. The proposed BIST circuit is designed using a 0.18 μm CMOS process in Cadence Virtuoso and verified with corner simulations.

An area efficient, high-frequency digital built-in self-test for analogue to digital converter

ABSTRACTA design of the digital built-in self-test (BIST) for an analogue to digital converter (ADC) is presented in this paper with the high-level description of static characteristics. The static characteristics of an ADC have modelled mathematically to develop the building blocks of the BIST. The design of digital BIST is focused on extended fault coverage, the best trade-off in area overhead, improvement in operating frequency and a reduction in power consumption. Proposed testing schemes are implemented using hardware description language and tested in ISE project navigator. The practical results of proposed digital BISTs are compared with the existing on-chip BIST circuits for performance analysis. Final uncertainty of the ADC output has been analysed using proposed testing schemes to detect the static errors. The simulator verifies the uncertainty of the data conversion from the static parameters computed by the BIST.

BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture

In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.

A Built-In Self-Test structure for measuring gain and 1-dB compression point of Power Amplifier

This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm.

A 76- to 81-GHz Multi-Channel Radar Transceiver

This paper presents a packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS for both long-range and short-range automotive radars. The chip contains a two-channel transmitter (TX), a six-channel receiver (RX), a local-oscillator (LO) chain, and built-in self-test (BIST) circuitry. Each transmit channel includes multiple variable-gain amplifiers and a two-stage power amplifier. Measured on-die output power per channel is +18 dBm at 25 °C, decreasing to +16 dBm at 125 °C. Each receive channel includes a current-mode mixer, followed by intermediate-frequency buffers. At 25 °C, measured on-die noise figure is 10–11 dB, conversion gain is 14–15 dB, and input 1-dB compression point exceeds +1 dBm. An integrated LO chain drives the transmit and receive chains and includes an 18.5- to 20.6-GHz voltage-controlled oscillator connected to cascaded frequency doublers and a divide-by-four prescaler. At 25 °C, measured phase noise is −100 dBc/Hz at 1-MHz offset from a 77-GHz carrier. Integrated BIST circuits enable the measurement of signal power, RX gain, channel-to-channel phase, and internal temperature. The chip is flip-chip packaged into a ball-grid array and extracted interconnect loss for the package is 1.5 to 2 dB. Total power consumption for the chip is 1.8 W from 3.3 V for a single-TX, six-RX mode.

A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit

ABSTRACT Built-in self-test (BIST) mechanism has been a very important approach for testing embedded memory's function and performance. In this paper, a high-speed BIST design for embedded static random access memory (SRAM) and one-port register file (RF) IPs testing was presented. With the purpose of achieving high-speed requirement, the pipe-line strategy is adopted in BIST circuit. Four SRAM instances and four one-port RF instances with the BIST circuit are integrated in a test chip. And the test chip has been fabricated in 28 nm low-leakage logical process. The final silicon data indicated that the proposed implementation is efficient and reliable for memory testing. Furthermore, the test result also show that the yield of memory instances with BIST circuits in the test chip reached up to nearly 100%.

Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers

We propose a self-test method for zero-IF radio frequency transceivers using primarily loopback, aided by a small built-in self-test (BIST) circuitry, to determine critical performance parameters, such as I/Q imbalance and nonlinearity coefficients. The transceiver is placed in the loopback mode by couplers, specifically designed to be asymmetric with respect to the primary path and the BIST path. The loopback path is also designed to include two traces with slightly different delays to enable parameter deembedding. Transceiver parameters are analytically computed using baseband I and Q signals over two frames, each of which is 200 μs in duration. Overall, measurement time is <;10 ms, including computation time. In addition to loopback hardware support and the associated parameter deembedding methodology, we propose a complimentary BIST circuit to measure the transmitter (TX) gain. The measured parameters can be used for predistortion or postdistortion to calibrate the transceiver, both at production time and in the field. Both simulation and hardware measurement results show that the proposed method can determine the target performance parameters with adequate accuracy for digital calibration. Measurement and the subsequent calibration are shown to reduce TX error vector magnitude more than fivefold, even for significantly impaired systems.

A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs

This paper investigates the capability of an architecture with digitally controllable gain and power consumption, for mitigating the effects of process variations on CMOS Low-Noise Amplifiers (LNAs). A 130-nm 1.2-V LNA with the proposed architecture is designed, based on the analysis of variability in LNAs with a traditional architecture under different biasing currents conditions, and the corresponding effects in the performance of a complete receiver context. Two different adjusting strategies are evaluated, which could be implemented with already reported Built-in Self-Test (BIST) circuits. Results show that the proposed architecture allows yield enhancement with low-power operation compared to traditional LNAs.

A Novel BIST Circuit for Testing and Analysis Parametric Faults in PLL

A novel built-in self-test (BIST) circuit of a phase-locked loop (PLL) in RF applications is presented in this paper. The proposed BIST circuit can detecting and analysis possible parametric faults in any block such as the phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage-controlled oscillator (VCO) and divide-by-N (DBN) of the PLL circuitry. The key advantage of this approach is that it insures that the PLL characteristics are not altered by adapting the BIST circuit. In order to reduce the chip area overheard, the proposed BIST circuit uses all existing blocks in PLL for measuring, analysis and testing parametric fault affected the circuit under test (CUT). The phase frequency detector circuit is used as a test stimulus generator and the oscillation frequency of VCO /divide-by-N circuit (DBN) as a measuring and analysis device. By building a test stimulus generator circuit and signature analyzer devices for the PLL, it can solve analog nodes loading problem and facilities the test accessibility. Fault simulation results indicate the characteristics of the proposed BIST circuit for detecting parametric faults, namely, excellent fault coverage (100%).