Built-in Self-test Circuit Research Articles

Transition faults detection in bit parallel multipliers over GF(2 m )

In this article, a C-testable design for detecting transition faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m) is discussed. For 100 percent transition fault coverage, the proposed technique requires only 10 vectors, irrespective of multiplier size, at the cost of 6 percent extra hardware. The proposed constant test vectors which are sufficient to detect both the transition and stuck-at faults in the multiplier circuits can be derived directly without any requirement of an ATPG tool. As the GF(2m) multipliers have found critical applications in public key cryptography and need secure internal testing, a Built-in Self-Test (BIST) circuit may be used for generating test patterns internally. This will obviate the need of having three extra pins for the control inputs and also provides public-key security in cryptography. Area and delay of the testable circuit are analyzed using Synopsys® tools with 0.18µ CMOS technology library from UMC.

BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops

This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

A new built-in self-test (BIST)-based diagnosis scheme for field programmable gate array (FPGA) interconnect delay faults is proposed. Faulty paths can be located after configuring the output response analyser of the BIST circuit as a scan chain. By analysing these faulty paths, segment fault candidates can be obtained. The proposed diagnosis scheme can find effective test paths to locate faulty segment candidates. Experimental results for an island-style FPGA show high diagnosis resolution in locating the faulty paths, under single- and double-fault models caused by single and double defects, respectively.

A New Approach for Built-in Self-Test of 4.5 to 5.5 GHz Low-Noise Amplifiers

This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

A New Low-Cost RF Built-In Self-Test Measurement for System-on-Chip Transceivers

This paper presents a new RF built-in self-test (BIST) measurement and a new automatic-performance-compensation network for a system-on-chip (SoC) transceiver. We built a 5-GHz low noise amplifier (LNA) with an on-chip BIST circuit using 0.18-/spl mu/m SiGe technology. The BIST-measurement circuit contains a test amplifier and RF peak detectors. The complete measurement setup contains an LNA with a BIST circuit, an external RF source, RF relays, 50-/spl Omega/ load impedance, and a dc voltmeter. The proposed BIST circuit measures input impedance, gain, noise figure, input return loss, and output signal-to-noise ratio of the LNA. The test technique utilizes the output dc-voltage measurements, and these measured values are translated to the LNA specifications such as the gain through the developed equations. The performance of the LNA was improved by using the new automatic compensation network (ACN) that adjusts the performance of the LNA with the processor in the SoC transceiver.

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 µm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive.

Low-cost test technique using a new RF BIST circuit for 4.5–5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5–5.5GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.

An Efficient Built-In Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

Built-in redundancy analysis for memory yield improvement

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.

Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems

The analog built-in self-test (BIST) scheme, with stimulus generation and response extraction based on the /spl Sigma/-/spl Delta/ modulation, is proven to be quite effective for sampled-data systems. We show that the /spl Sigma/-/spl Delta/ modulators can be selected optimally for certain applications and functional tests. The criteria for valid tests are also derived. In particular, a valid frequency response test is determined by the frequency response observation range FROR/sub BIST/(z) of the BIST circuit. Given the transfer function H/sub CUT/(z) of the circuit under test, the requirement becomes FROR/sub BIST/(z)/spl Gt/|1/H/sub CUT/(z)|. Using the MOSIS 0.35-/spl mu/m CMOS process, we have implemented a test chip containing a Fleischer-Laker biquadratic low-pass filter as the circuit under test. An on-chip one-bit digital-to-analog converter provides the analog stimulus from a bit stream which is applied externally. For each test item, different bit streams, synthesized by first-, second-, and fourth-order /spl Sigma/-/spl Delta/ modulators that are programmed by software, are compared for performance. First- and second-order /spl Sigma/-/spl Delta/ modulators are implemented on the test chip as the candidates for the analog response extractor. The measurement results by single-tone tests and multitone tests validate the feasibility of the BIST scheme.

Modeling Fault Coverage of Random Test Patterns

We present a new probabilistic fault coverage model that is accurate, simple, predictive, and easily integrated with the normal design flow of built-in self-test circuits. The parameters of the model are determined by fitting the fault simulation data obtained on an initial segment of the random test. A cost-based analysis finds the point at which to stop fault simulation, determine the parameters, and estimate fault coverage for longer test lengths. Experimental results on benchmark circuits demonstrate the effectiveness of this approach in making accurate predictions at a low computational cost. As compared to the cost of fault-simulating all the test vectors, the savings in computational time for larger circuits ranged from four to fourteen times. We also present an analysis of the mean and the variance of the fault coverage achieved by a random test of a given length. This analysis and simulation results demonstrate that while the mean coverage is determined by the distribution of the detectabilities of individual faults, the dual distribution of fault coverage of individual test vectors determines the variance.

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories

The authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are March based, which have linear time complexity and result in a simple built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns to test the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multibackground March algorithms have shorter test lengths than previously reported ones, and the diagnostic test algorithm guarantees 100% diagnostic resolution for NPSFs and conventional RAM faults. Based on the proposed algorithms, the authors also present a cost-effective BIST design. The BIST circuit is programmable, and it supports March algorithms, including the proposed multibackground one.

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.

Improving the Timing of Extended Finite State Machines Via Catalyst

We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of catalyst, adds a functionally redundant block—which includes a piece of combinational logic and several other registers—to the circuits under consideration so that the timing critical paths are divided into stages. During this transformation, the circuit′s functionality is not affected, while the speed is improved significantly. This technique has been successfully applied to an industrial application—a Built‐In Self‐Test (BIST) circuit for static random access memories (SRAMs). The synthesis result indicates a 47% clock cycle time reduction.

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.

A new approach to built-in self-testable datapath synthesis based on integer linear programming

The focus of high-level built-in self-test (BIST) synthesis is register assignment, which involves system register assignment, BIST register assignment, and interconnection assignment. To reduce the complexity involved in the assignment process, existing high-level BIST synthesis methods decouple the three tasks and perform the tasks sequentially at the cost of global optimality. They also try to achieve only one objective: minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we propose a new approach to the BIST data path synthesis based on integer linear programming that performs the three register assignment tasks concurrently to yield optimal designs. In addition, our approach finds an optimal register assignment for each k-test session. Therefore, it offers a range of designs with different figures of merit in area and test time. Our experimental results show that our method successfully synthesizes a BIST circuit for every k-test session for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.

In-sawing-lane multi-level BIST for known gooddies of LCD drivers

Liquid crystal display (LCD) drivers usually operate at low speed, and have a low input-count but high output-count with multilevel voltages. A novel built-in-self-test (BIST) method for LCD drivers is proposed to reduce testing costs. This BIST circuit will be placed in the sawing lanes to reduce the chip area. The chip overhead and the testing costs are reduced, while the test coverage can be maintained.

Redundancy and testability in digital filter datapaths

Test issues in application-specific digital filter datapaths are investigated. It is found that such designs can contain hundreds of redundant faults, making it difficult to accurately determine fault coverage. Since these redundant faults tend to appear in the same general location as test-resistant faults, the presence of many redundant faults can hide significant untested faults despite high overall test coverage. Classes of redundant faults that arise in digital filter datapaths are described, and we propose a suite of techniques for identifying and eliminating the most common redundancies based on arithmetic optimization. The approach is suitable as a front-end to more accurate fault simulation, or can be used in the design process to eliminate redundant logic. The approach is validated as a tool for developing very high-coverage built-in self-test circuits, showing that 100% fault coverage can be achieved in 24k-gate filters with as little as 1% area overhead. When used as a datapath optimization technique, the average area reduction over 15 designs was 8.9%, compared with moderately optimized designs. As a front-end to fault simulation, the approach yielded a 97.9% average reduction in the number of undetected faults across the 15 designs.

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.

A built‐in self‐test structure for arithmetic execution units of VLSIs

AbstractThis paper proposes advanced built‐in self‐test (BIST) structures: a bit‐distributed pattern generator (BDPG) and a multistage space compressor (MSSC) for arithmetic execution units of VLSIs. By focusing on the regularity of the arithmetic execution units, the required area overhead of the BIST circuits is less than that of conventional ones. The experimental result shows that these structures can reduce almost 60 percent of the hardware overhead of conventional BIST circuits while maintaining high‐fault coverage. These BIST configurations will make a significant contribution to test cost reduction for the performance‐orientation digital LSIs, especially digital signal processor LSIs.