Body Bias Technique Research Articles

Stability analysis of Sub-threshold 6T SRAM cell at 45 nm for IoT application

In ultra-Low power application the supply volt- age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv.

Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of supply. The result showed the reduction of VBB technique in term of peak power, and average power, compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

W-band CMOS direct injection-locked frequency divider with 23.5-GHz locking range using distributed LC network and power matching and body bias techniques

A low power and wide locking-range W-band (75–110 GHz) divide-by-2 direct injection-locked frequency-divider (DILFD) using standard 90 nm CMOS technology is reported. To enhance the operation frequency, distributed LC network is used as the load of the crossed-coupled transistors. To improve the input sensitivity, a power matching network is included at the injection terminal of the switch transistor. In addition, to enhance the frequency locking range, body bias technique (i.e. a body resistor in conjunction with a zero body-source bias) is adopted in the switch transistor to reduce its threshold voltage. The result shows that a wide locking-range of 23.5 GHz [from 69.5 to 93 GHz (28.9%)], covering the 77–81-GHz-band for short range automotive radar system and 81–86-GHz-band for high-speed point-to-point wireless communication access system, was achieved. The DILFD can be operated at a low input power of − 35 dBm, one of the best input sensitivity ever reported for a W-band CMOS divider. The power consumption of the DILFD was only 3 mW from a 0.7 V power supply. The chip area was only 0.76 × 0.66 mm2 excluding the test pads.

Dynamic Control of AlGaN/GaN HEMT Characteristics by Implementation of a p-GaN Body-Diode-Based Back-Gate

We report on the implementation of dynamic body-bias technique to improve the performance of AlGaN/GaN high electron mobility transistors (HEMTs) with the successful integration of body-diode. In this configuration, p-GaN body-diode-based back-gate control is used to shift the threshold voltage and dynamically modulate the ON/OFF characteristics of a normally-ON AlGaN/GaN HEMT. A fourth back-gate terminal is connected to the p-GaN layer to control the depletion width of the body-diode, which in turn modulates the 2-D electron gas (2DEG) density. A positive/negative shift in the threshold voltage is measured by increasing/decreasing the depletion width below the channel. A positive back-gate bias application in the ON-state is shown to increase the 2DEG current density resulting in higher ON-current. The application of a negative back-gate bias is shown to be effective in the positive shift of the threshold voltage, in reducing the 2DEG channel current and in increasing the OFF-state break-down voltage. We have experimentally demonstrated enhanced effect of body-diode-based back-gate control in shifting the threshold voltage of a normally-ON HEMT toward normally-OFF mode. The optimum back-gate voltage range which can be applied during both ON and OFF states has been experimentally determined.

A 167‐to‐172 GHz 65‐nm CMOS body‐voltage‐tuned harmonic‐mode voltage‐controlled oscillator

Abstract This article presents a mm‐wave harmonic‐mode varactor‐free 167‐to‐172‐GHz oscillator that features improved output power and tuning range. The parasitic capacitor of the cross‐coupled pair is adjusted for frequency tuning via the body‐bias technique, thus eliminating the need for varactors of conventional mm‐wave voltage‐controlled oscillators (VCOs). The output of the proposed VCO is at the 2nd‐harmonic and is tunable from 167 to 172 GHz, while its dc power consumption ranges between 13.5 and 21 mW, respectively. The proposed circuit was designed and implemented using TSMC 65‐nm 1P9M CMOS technology, with a total chip size of 0.22 × 0.35 mm2. The output power of the proposed VCO is −10.5 dBm at 169.8 GHz with 13.5 mW dc power consumption, and its maximum dc‐to‐RF efficiency is 0.48%.

Common source power amplifier design for 5G application in 28-nm UTBB FD-SOI technology

The telecommunication market examines a highly growing demand for RF mobile devices where low latency and high performance are ongoing improvement. The power amplifier (PA) is a major element of the radio frequency front-end; especially if power consumption and bandwidth are considered. This paper presents the design of 5G mm-wave PA using both Common Source Class-AB and Class-J topologies utilizing 28-nm UTBB FD-SOI technology and its body bias technique. Upon taking into consideration the parasitic extraction of the transistor, RF pads, and interconnection to ground, a comparison is made and the theoretical effectiveness of Class-J topology for single stage large signal amplification is simulated. Moreover, two distinct transistors - widths of 250 µm and 350 µm - are simulated where each has its own topology in order to study the impact of increasing the width on the performance of the PA. The stability of the designed Power Amplifiers is taken into consideration and the unconditional stability conditions are approved. While 5G spectral band is not yet specified and determined, recent studies proved that the 28 GHz band is particularly effective for 5G mobile standardization.

High performance 9T adiabatic SRAM and novel stability characterization using pole zero placement

Stability of memory cells always considered as a most significant figure for defining the logic data at output terminals. And the value of logic data is influenced due to the dominance of leakage component at deep submicron technology. Stability analysis and leakage issues of new 9T adiabatic static random access memory (SRAM) cells is presented using the technique of pole zero concept. With the help of flow graph characteristic of memory cell is modeled and validated using MATLAB tool. The elementary cell of proposed SRAM resembles behavior of 4T-SRAM consisting of two high load resistors constructed of PMOS and cross-coupled NMOS pair. NMOS switch is used to restrict short circuit current and two gradually rising and falling wave pulses with controlled switching current flow. The simulation is carried out at 180 nm technology and it has been found that the average power dissipation of the proposed SRAM reduces by a factor of 41 with no performance degradation and energy is efficiently recovered using adiabatic and body biasing technique.

Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications

The Internet of Things is an emerging application area which is going to become one of the leading electronic hubs in the semiconductor industry. The IoT systems require battery-enabled energy-efficient memory circuits to operate at ultra-low voltage (ULV). In this paper, a novel Schmitt trigger-based, single-ended 7-Transistor (7T) Static Random Access Memory (SRAM) cell which uses dynamic body bias technique for IoT applications is presented. The proposed 7T SRAM cell is designed using standard 45nm Complementary Metal Oxide Semiconductor technology at an ULV of 0.3V. The post-layout simulation results have shown more than 22% improvements in the Read Static Noise Margin and more than 44% write, 63% read energy savings in comparison with the conventional 6T cell, 7T, single-ended 8T, and Schmitt trigger 11T cell designs. The proposed design is also found to be stable at different process corners and supply voltages. A new quality metric SNM per unit Area to Energy Ratio which evaluates the overall performance of the SRAM cell design is calculated and is found to be highest for the proposed design.

A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

A digital cell library operating in the near-threshold voltage (NTV) region is presented to obtain both high energy efficiency and optimized performance. The proposed library oriented to the NTV region is optimized using the parasitic effects of nanometer process technology and a body-biasing technique. To maximize the energy efficiency, the proposed cell library utilized the minimum width allowed by the process as the base width unit. To enhance the performance, digital cells were developed with various strengths whose sizing method relies on the minimum unit width, reverse short channel effect, and inverse narrow width effect. An asymmetric gate-length scheme is applied to multi-fan-in logic gates to increase the performance. Also, the proposed TAP cell was added, combined with an inverter-based forward body-biasing circuit. Finally, a library with 59 cells was developed and made available for synthesis and automatic layout and the proposed NTV library was then evaluated with ISCAS benchmark logics. The proposed NTV cell library shows more than 10~20% less energy consumption compared with a conventional digital cell library using minimum gate length and monolithic width. EDP is also increased by 10~20% with a simply controlled body-biasing scheme compared with the conventional one.

A low power current-reuse LC-VCO with an adaptive body-biasing technique

This work presents a low-power low-phase noise current-reuse LC voltage controlled oscillator (VCO) with an adaptive body-biasing technique that enhances the reliability of the proposed circuit under process, voltage, and temperature (PVT) variations. Furthermore, the supply voltage and power consumption of the proposed VCO are reduced by the start-up oscillation condition that is provided by the adaptive body-biased circuit. This property is in fact very interesting from the power management perspective. The proposed VCO works at carrier frequency of 1.8 GHz and draws the power of only 306 µW from a 0.9 V supply. It achieves phase noise of −123.36 dBc/Hz at 1 MHz offset and provides a figure-of-merit (FoM) of −193.61 dBc/Hz. The post-layout simulation results of designed VCO in 0.18 µm standard CMOS technology confirm the effectiveness of the proposed circuit.

A Low Power 2.4 GHz CMOS Mixer Using Forward Body Bias Technique for Wireless Sensor Network

Wireless sensor network (WSN) is a highly-demanded application since the evolution of wireless generation which is often used in recent communication technology. A radio frequency (RF) transceiver in WSN should have a low power consumption to support long operating times of mobile devices. A down-conversion mixer is responsible for frequency translation in a receiver. By operating a down-conversion mixer at a low supply voltage, the power consumed by WSN receiver can be greatly reduced. This paper presents a development of low power CMOS mixer using forward body bias technique for wireless sensor network. The proposed mixer is implemented using CMOS 0.13 μm Silterra technology. The forward body bias technique is adopted to obtain low power consumption. The simulation results indicate that a low power consumption of 0.91 mW is achieved at 1.6 V supply voltage. Moreover, the conversion gain (CG) of 21.83 dB, the noise figure (NF) of 16.51 dB and the input-referred third-order intercept point (IIP3) of 8.0 dB at 2.4 GHz are obtained. The proposed mixer is suitable for wireless sensor network.

Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power

The static power consumption is an important parameter concern in IC design due to t for a higher integration numbers of transistor to achieve greater performance in a single chip. Leakage current is the main issues for static power dissipation in standby mode as the size of transistor been scale. Therefore, the subthreshold leakage current rises due to threshold voltage scaling and gate leakage current increases due to scale down of oxide thickness. In this paper, a Variable Body Biasing (VBB) technique was applied to reduce static power consumption in VLSI design. The VBB technique used a DC bias at body terminal to control the threshold voltage efficiently. The Synopsys Custom Designer EDA tools in 90nm MOSFET technology was used to design a 1-bit full adder with VBB technique in full custom methodology. The simulation of 1-bit full adder was carried out with operation voltage supply was compared in conventional technique and VBB technique. The results achieved the reduction in term of peak power, and average power, in static CMOS 1-bit full adder compared with conventional bias and VBB technique.

75–110-GHz $W$ -band High-Linearity Traveling-Wave T/R Switch by Using Negative Gate/Body-Biasing in 90-nm CMOS

In this letter, a 75-110-GHz W-band high-linearity traveling-wave single-pole-double-throw switch in 90-nm CMOS GUTM 1P9M is presented. Compared with the traditional traveling-wave switch with negative body-biasing technique, the proposed design applies the negative biasing to the gate terminals simultaneously. Therefore, the third-order intermodulation product is significantly reduced. The measured results show that the insertion loss is less than 3.4 dB, return loss is better than 10 dB, and Tx-to-Rx isolation is higher than 40 dB, respectively. For the linearity of the switch, the measured IP1dB is higher than 15 dBm and IIP3 is 37.1 dBm at 94 GHz, respectively. The proposed switch presents good performance of insertion loss, isolation, IP1dB, and IIP3, among the compared millimeter-wave CMOS switches.

A Fully-integrated Highly Efficient CMOS Class-E Power Amplifier Using Cascode Class-E Drivers for WLAN Applications

This paper presents a modified class-E single-ended power amplifier (PA) for WLAN application. The proposed class-E PA consisting of two stages, all driver stages adopts bias voltage technique to simplify the structure and improves RF performance. The driver stage adopts the forward body bias technique to lower threshold voltage and realize high efficiency with low operation voltage; the power stage utilizes cascode topology with a self-biasing voltage technique to reduce device stress. The proposed PA is simulated by cadence IC in TSMC 0.18-μm CMOS technology. With a 2.3 V supply voltage, the fully integrated CMOS PA achieves maximum output power of 27.8 dBm and power-added efficiency (PAE) of 48.3% at 2.4GHz. It achieves high power gain of 31.5 dB and large output power with low input signal. The chip area of the proposed class-E PA is 0.90 mm2.

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

SummaryA fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM

Spin-transfer torque magnetic random access memory (STT-RAM) is a promising and emerging technology due to its many advantageous features such as scalability, nonvolatility, density, endurance, and fast access speed. However, the operation of STT-RAM is severely affected by environmental factors such as process variations and temperature. As the temperature rockets up in modern computing systems, it is highly desirable to understand thermal impact on STT-RAM operations and reliability. In this paper, a thermal-aware MTJ model, calibrated and validated by experimental measurements, is proposed as the basis for thoroughly thermal aware analysis of a 1T1MTJ STT-RAM cell structure. Using this model, we investigate temperature effect on memory cell access behavior in terms of access latency, energy, and reliability on a 45-nm technology node. Thermal impact on a more advanced 11-nm technology node is also evaluated in the paper. Additionally, we propose a thermal-aware design for STT-RAM sensing circuit using a body-biasing technique, which can enlarge read margin dramatically to enhance read reliability under temperature variations. Moreover, our proposed technique can suppress read disturbance effectively as well. Experimental results show that our proposed sensing circuit can enlarge read margin by 2.47 $\times$ when reading “0” and 3.15 $\times$ when reading “1,” and reduce read disturbance error rate by 55.6% on average.

Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions

Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model.

Effect of reverse body bias on hot-electron-induced punchthrough reliability of pMOSFETs with thin gate dielectric at high temperatures

The effect of the reverse body bias VSB on the hot-electron-induced punch-through (HEIP) reliability of pMOSFETs with a thin gate dielectric at high temperatures was investigated for the first time. Experimental results indicate that the reverse VSB increased the HEIP degradation for a thin pMOSFET because of the increase in the maximum electric field Em due to the increase in the threshold voltage Vth. The sensitivity of HEIP degradation to VSB increased with increasing body effect coefficient γ at a given oxide thickness Tox. However, a thin device (22 Å) showed a much stronger dependence of HEIP degradation on VSB due to the decrease in the velocity saturation length l, although it had a smaller γ than a thick device (60 Å). These new observations suggest that the body bias technique for improving circuit performance can cause a reliability problem of nanoscale pMOSFETs at high temperatures and impose a significant limitation on CMOS device scaling.

DTMOS-Based Pulse Transformer Boost Converter With Complementary Charge Pump for Multisource Energy Harvesting

An energy-harvesting system that accommodates both discrete-time or continuous-time energy sources simultaneously is presented. The core dc–dc converter is a pulse transformer boost converter using dynamic threshold MOS transistor that self-starts at 36 mV-input voltage and generates bipolar output voltages up to ±2.5 V. Employing the dynamic body bias technique to the boost converter power transistor improves power efficiency at sub-300-mV input voltages up to two times over the identical transistor in a conventional configuration. At large harvested power, the source-to-body diode of the power transistor functions as an input voltage limiter. Dynamic threshold MOSFET (DTMOS) also increases transistor saturation current and output power compared to conventional transistors at similar input voltage. Instead of using a linear shunt regulator, excess power is dissipated by internal loss of a bipolar-clocked cross-coupled charge pump. An on-chip voltage-controlled oscillator, which generates clock frequency in proportion to the harvested power, and a unipolar-to-bipolar level shifter are included to drive the charge pump designed. The circuit prototypes are fabricated by using the UMC 0.13- $\mu\mbox{m}$ CMOS process with the triple-well option.