Body Bias Technique Research Articles

A Simulation Study of Colpitts Oscillator Reliability and Variability

Nanoscale CMOS reliability and process variation effect on the LC Colpitts oscillator has been examined. Mixed-mode device and circuit simulation is used to investigate the physical insight of impact ionization to the Colpitts oscillator. An analytical equation of phase noise as a function of offset frequency, transistor parameters, and body bias has been derived. The analytical predictions are in good agreement with ADS simulation results. An adaptive body bias to minimize process variation effect on the Colpitts oscillator has also been proposed. The adaptive body bias technique effectively reduces the hot electron effect and process variability on the Colpitts oscillator performance, as supported by Monte Carlo simulation results.

Dual cross-coupling LNA with forward body bias technique

A fully integrated low-power LNA with dual cross-coupling and forward body bias (FBB) techniques is presented. The first cross-coupling circuit is applied at the transconductance stage. By connecting body nodes to each other's source terminals, the body cross-coupling network forms the gate-driven and body-driven simultaneously input stage to gain its effective transconductance, which in turn improves the noise performance and decreases current consumption. In addition, the second capacitor cross-coupling configuration is applied at the input stage to form a feed-forward connection, which results in not only boosting the effective transconductance, but also reducing the influence of the gate noise from the input transistors as well. Moreover, to decrease the overall power consumption further, the FBB technique is employed to lower the supply voltage. The measured noise figure is lower than 3.38 dB and the core circuit consumes only 2.16 mW.

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits

The challenges to design engineers have been complicated due to the introduction of nanoscale process variation into the design phase. One of the ways to analyze the circuit behaviors under process variation is to determine the rare events that may be originated due to such process variation. A method called Statistical Blockade (SB) had been investigated to estimate the rare events statistics especially for high-replication circuits [1]. An enhanced statistical blockade method is proposed in this paper which is shown to be much faster compared to the traditional exhaustive Monte Carlo simulation. In SB, the classification threshold determination is quite important for different tail regions which is related to the number of rare events simulation. This paper presents the values of classification threshold tc for different tail regions of typical circuits and the training samples size n required for corresponding tc. It offers both fastest speed of simulation and highest accuracy for the proposed Statistical Blockade method. It is also proven that the obtained tc can be used for all the technology corners. The enhanced statistical blockade method thus performs fast estimate the robustness for different designs. In the proposed method, the tail part of the whole distribution is used in estimation; thereby saving time. It shows 7.3× faster than traditional evaluation methods. Furthermore, for the design which is proved to be robust even in worst-case, the optimal body bias voltage is applied to improve the performance and power while reducing the variability with Adaptive Body Bias (ABB) technique. Index Terms Statistical Blockade Method, Robustness Circuits, Nanoscale CMOS, Arithmetic Circuits, Monte Carlo, Rare Event

High‐performance low‐power 27‐GHz CMOS voltage‐controlled oscillator for Ka‐band applications

AbstractA new low‐power 27.07‐GHz voltage controlled oscillator is designed for Ka‐band applications in this article. Body bias technique is used for the low‐power and low‐phase noise VCO design. The VCO can be tuned from 26.35 to 27.102 GHz. The measured phase noise is −106.2 dBc/Hz at 1 MHz offset from the carrier frequency. The corresponding figure‐of‐merit (FOM) is calculated to be −183.2 dBc/Hz. The VCO is implemented with the TSMC 0.18 μm one‐poly‐six‐metal 1.5 V mixed signal/RF CMOS technology. The chip size is 0.565 × 0.69 mm2. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2872‐2875, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26433

CMOS direct injection-locked frequency divider (3.55 mW 80 GHz) with 26.3% locking range using distributed LC tank and body bias techniques

A 3.55-mW 80-GHz complementary metal-oxide-semiconductor (CMOS) divide-by-2 direct injection-locked frequency divider (DILFD) using distributed inductance-capacitance (LC) tank and body bias techniques for operation frequency and locking-range enhancement is demonstrated.Compared with the traditional LC tank, the distributed LC tank significantly decreases the equivalent LC and C values. This in turn results in an increase of the operation frequency and the locking range. In addition, trans-conductance (gm) of the injection transistor can be improved by body bias due to the reduction of its threshold voltage. This in turn results in an increase of the locking range (6.2 GHz in simulation). Furthermore, power consumption is reduced by eliminating the head current source in the traditional DILFD. Measurement result shows the proposed DILFD achieved a state-of-the-art 26.3% (61.5–80.1 GHz) locking range and an excellent output phase-noise of −128.69 dBc/Hz at 1 MHz offset. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2694–2697, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26333

A 53-67 GHz low power and wide locking range injection-locked frequency divider with forward body bias

A 53–67 GHz wide locking range injection-locked frequency divider (ILFD) has been designed and fabricated using 0.13-μm CMOS process.By using forward body bias technique, the proposed ILFD demonstrates good performance of the wide locking range while maintaining low DC power consumption. Via a 0 dBm incident signal power, an input locking rage greater than 14 GHz (>23%) is achieved with 4 mW from supply voltage of 0.8 V. If the supply voltage further reduces to 0.6 V, the input locking rage is 6 GHz (10%) while consuming only 1.2 mW. Compared to previous reported works in high-speed CMOS FD, the presented ILFD achieves superior figure of merit (FOM). Without extra voltage control mechanisms to increase the locking range, this FD covers whole 57–64 GHz band is suitable for integration into a 60 GHz WPAN phase-locked loop system. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1386–1389, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25989

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

To compensate the variability effects in advanced technologies, Process, Voltage, Temperature (PVT) monitors are mandatory to use Adaptive Voltage Scaling (AVS) or Adaptive Body Biasing (ABB) techniques. This paper describes a new monitoring system, allowing failure anticipation in real-time, looking at the timing slack of a pre-defined set of observable flip–flops. This system is made of dedicated sensor structures located near monitored flip–flop, coupled with a specific timing detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45nm low power technology, demonstrate a scalable, low power and low area system, and its compatibility with a standard CAD flow. Gains between an AVFS scheme based on those structures and a standard DVFS are given for a 32bits VLIW DSP.

Subthreshold Schmitt trigger using body-bias technique for ultra low power and high performance applications

Digital subthreshold logic provides extremely low power consumption since the power supplies are kept below the threshold voltage and using the small subthreshold current of MOS transistors to operate. In this paper, a body-bias technique to match the subthreshold currents of both the NMOS and PMOS transistors is explored and a Schmitt trigger circuit employing this bias technique is proposed. Extensive circuit simulations were conducted and the results were compared with standard body bias technique in terms of performance parameters. The simulation results were obtained with 0.18 μm technology parameters. The conclusion is that Schmitt trigger with this body biasing is suitable for high performance and ultra low power applications.

Level shifter for low power applications with body bias technique

In present work three new designs of level shifter in 0.35μm technology using body bias approach have been presented. The level shifters, namely conventional type-I, conventional type-II and contention mitigated have been improved by varying the reverse body bias from 0.1V to 0.5 V. Circuits have been simulated in Spice with TSMC0.35 process technology. Output level of 3.3V has been obtained with input pulse of 1.6V. Modified conventional type-I level shifter shows minimum power consumption of 90.1250pW as compared to 498.33pW for conventional type-I. Further, modified conventional type-II gives minimum power of 480.28pW as compared to 3479pW with existing circuit. Third proposed circuit namely modified contention mitigated level shifter (CMLS) show minimum power consumption of 85.52pW as compared to 493.73pW for circuit without modifications. Simulation results show that proposed circuits are able to shift 1.6V to 3.3V with reduced power consumption with little conciliation in delay. International Journal of Engineering, Science and Technology, Vol. 2, No. 6, 2010, pp. 297-305

NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.

An Implementation of Integral Low Power Techniques for Modern Cell-Based VLSI Designs

Recent research has proposed several low-power design techniques for VLSI circuitry in nano-scale CMOS era. However, these techniques always involve custom layout design or novel Electronic Design Automation (EDA) flows. In this paper essential low power techniques such as voltage separation, body bias and power switch are implemented in existent place and route (P&R) tools. These techniques enable the possibility to integrated low power techniques into standard Cell-Based physical design flow. The result of these research shows a little overhead in design procedure equally area overhead compare with fully custom design flow. The proposed low power design techniques can be cooperated with modern power management system to enable the power reduction in targeting circuitry with small implementation overheads. disconnect power supply of functional block. This is achieved by connecting a transistor in series with the power supply of the block (3). In practice, a network of power switch may be necessary to efficiently control and reduce leakage power. Another dynamic technique, body bias, needs dynamically changing the body bias applied to the block (4). During active mode, forward body bias (FBB) is applied to increase the operating frequency. Alternately, reverse body bias (RBB) can be applied during idle mode for further leakage savings. This body bias technique can be combined with a power switch to provide even further leakage power savings. However, the majority of low power design circuits are implemented with Fully-Custom design. In order to automate design phase and satisfy the demand of Time-To-Market requirement, integrating low power techniques into Cell- Based physical design flow is essential. In order to apply the benefits offered by low leakage techniques into Cell-Based design, some physical design issues must take into considerations. Therefore, the general physical design flow must be modified for the integrating low power techniques into physical design. In this paper, a low power physical design methodology is presented. By using this low power design methodology, a Cell-Based design circuit with low power techniques features is available. Our goal is to create a regular physical design flow utilizing existent EDA tool.

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8bit pipelined multiplier operating at 320MHz under 0.5V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5V. The proposed pipelined multiplier is fabricated in 130nm CMOS process. It operates up to 320MHz and the power consumption is only 1.48mW at 0.5V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5V is reduced over 5.7 times than that of the traditional architecture at 1.2V. Thus, the proposed 8×8bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.

A Low Loss High Isolation DC-60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process

In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using the negative body bias technique. Moreover, the insertion loss, the input 1 dB compression point (P1 dB)> and the third-order intermodulation (IMD3) of the switch are all improved. With the technique, the switch demonstrates an insertion loss of 3 dB and an isolation of better than 48 dB from dc to 60 GHz. The chip size of the proposed switch is 0.68 × 0.87 mm2 with a core area of only 0.32 × 0.21 mm2.

ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Subthreshold operation of digital circuits has emerged as a promising approach to achieve ultralow power dissipation. However, extensive application of subthreshold logic is limited due to low performance and high susceptibility to process variation (PV). This paper proposes a PV-tolerant ultradynamic voltage scaling (UDVS) system where performance requirements dictate whether the devices will work in the subthreshold or superthreshold region. Due to different mechanisms of current conduction, it is necessary to use different <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios for different regions of operation to improve circuit robustness, performance, and power. With an analytical model of circuit robustness, we present an adaptive body-biasing technique to dynamically adjust the ß-ratio depending on the operating region. Measurements show that our methodology improves the dynamic range of operation the circuits-from 1.2 V all the way down to 85 mV consuming 40 nW (at 85 mV) of power for an 8 × 8 finite-impulse response filter fabricated in a 0.13-¿m technology, and can salvage circuits which otherwise would fail to operate due to device mismatches and skewed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios.

Low-Voltage Wireless Analog CMOS Circuits toward 0.5 V Operation

This paper introduces several techniques for achieving RF and analog CMOS circuits for wireless communication systems under ultra-low-voltage supply, such as 0.5V. Forward body biasing and inverter-based circuit techniques were applied in the design of a feedforward Δ-Σ A/D modulator operating with a 0.5V supply. Transformer utilization is also presented as an inductor area reduction technique. In addition, application of stochastic resonance to A/D conversion is discussed as a future technology.

An E-TSPC Divide-by-2 Circuit With Forward Body Biasing in 0.25 $\mu$m CMOS

A forward body biasing (FBB) technique is employed by an extended true-single-phase-clock (E-TSPC) divide-by-2 circuit in 0.25 mu m CMOS for an efficient on-chip control of power and speed. By applying the forward body bias voltage of 0.4 V, the maximum operating frequency is improved by 78% while the current dissipation is increased only by 21%. As a result, the divider figure-of-merit is improved by 46%. The phase noise however is not significantly affected by the forward body biasing. We believe that the FBB technique can be an efficient means for on-chip scaling of speed and power in E-TSPC RF frequency divider circuits.

Leakage reduction, delay compensation using partition-based tunable body-biasing techniques

In recent years, fabrication technology of CMOS has scaled to nanometer dimensions. As scaling progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle the problems of process variations and leakage current, an effective way is to use a body-biasing technique. In substance, using the RBB technique can minimize leakage current but increase the delay of a gate. Contrary to RBB, the FBB technique decreases the delay but increases leakage current of a gate. In the previous work, a single body-biasing is applied to the whole circuit. In a slow circuit, since the FBB is applied to the whole circuit, the leakage current of all gates in the circuit increases dramatically. On the other hand, in a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body-biasing is restricted by the critical paths, and the saving of leakage current is limited. In this article, we propose a design flow to partition the circuit into subcircuits so that each subcircuit can be applied its individual RBB or FBB. Experiments show that our method is able to save leakage current from 42% to 47% as compared to designs not using a body-biasing technique. Under process variations, our method can save 42% to 49% leakage on fast circuits and 20% to 35% on slow circuits.

A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control

Dynamic Voltage Scaling (DVS) and Adaptive body bias (ABB) techniques respectively try to reduce the dynamic and static power components of an integrated circuit. Ideally, the two techniques can be combined to find the optimal operating voltages (VDD and VBB) to minimize power consumption. A combination of the DVS and ABB may warrant the circuit to operate at voltages (supply and body bias) different from the values specified by the two methods working independently. Also, this VDD and VBB values for minimal power consumption varies with the workload of the circuit. The workload can be used as an index to select the optimal VDDNBB values to minimize the total power consumption. This paper examines the optimal voltages for minimal power operation for typical data path circuits like adders and multiply-accumulate (MAC) units across various process, voltage, and temperature conditions and under different workloads. In addition, a workload based look up table to minimize the power consumption is also proposed. Simulation results for an adder and a multiply-accumulate circuit block indicate a power saving of 12-30% over standard DVS scheme.

Analysis and Design Techniques of CMOS Charge-Pump-Based Radio-Frequency Antenna-Switch Controllers

Analysis and design techniques of charge-pump-based RF antenna-switch controllers are presented. Loading effects of RF antenna switches that cause voltage drop of the controller have been identified and embedded in the analysis. The proposed analysis also captures effects of MOS-switch on-resistance and parasitic capacitances, so more precise descriptions of the charge-pump output voltage can be obtained. Furthermore, the body biasing technique has been employed to prevent latch-up. The analysis and the design techniques have been verified using a 0.35-mum CMOS technology. RF antenna-switch performances with the designed controller have also been measured and presented.