Bipolar Gain Research Articles

The inversion channel resonant-cavity enhanced photodetector for two-dimensional optoelectronic array applications

The operation of the inversion-channel resonant-cavity enhanced (RCE) photodetector in a configuration compatible with the vertical-cavity surface-emitting laser (VCSEL) is discussed. The phototransistor uses three strained InGaAs/GaAs quantum wells as the absorbing region and a post-growth dielectric top stack. A quantum efficiency of 41% was obtained at the resonant wavelength of 0.94 mu m, thereby giving a resonant-enhancement factor of 13.5. A bipolar transistor gain of 6.8 at a current density of 10 A/cm/sup 2/ allowed the phototransistor responsivity to reach 2.1 A/W at the resonant wavelength. >

An SEU resistant 256 K SOI SRAM

A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256 K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 degrees C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10% worst-case error rate of 3.4*10/sup -11/ errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition. >

The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 mu m SOI devices. This can pose severe constraints in future 0.1 mu m SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain beta of SOI devices without using a body contact.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multistable floating body potentials: The cause of hysteresis in silicon-on-insulator metal-oxide-semiconductor transistors

An experimental study of the hysteresis ID-VG characteristics in n-channel silicon-on-insulator metal-oxide-semiconductor transistors is reported. The result shows that the hysteresis is induced by multistable floating body potentials. An analytical model, which is based on the nonlinear feedback of carrier generation via multiplication and carrier discharge through parasitic bipolar action, also reveals that multistable floating body potentials are responsible for the hysteresis in ID-VG characteristics. To alleviate hysteresis effect, it is essential to reduce the parasitic bipolar current gain α and multiplication factor M. The reduction of α and M can be achieved by optimal source/drain design.

Suppression of parasitic bipolar effects in thin-film SOI transistors

In order to correctly estimate the bipolar holding voltage of thin-film SOI transistors with submicrometer gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionization. The bipolar current gain was found to be strongly dependent upon bandgap narrowing in the heavily doped source, while impact ionization may be most accurately modeled with a nonlocal ballistic model employing a composite electron mean-free path of 9.2 nm. Simulation with the improved models suggests that a reduction in the lateral electric field of the n/sup -/ drain region, and hence an increased bipolar holding voltage, may be achieved by using ultrathin highly doped SOI films. For a 0.5- mu m gate length, a maximum holding voltage in excess of 6 V has been simulated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Berkeley reliability simulator BERT: an IC reliability simulator

BERT (Berkeley reliability simulator) is a CAD tool developed for the purpose of design for reliability. This paper describes its intended application, the physical models and approaches used to simulate the hot electron effect, oxide time-dependent breakdown, electromigration, and bipolar transistor gain degradation.

IC reliability simulation

The motivation and challenges of IC reliability simulation are discussed. The reliability simulator BERT is used to illustrate the physical models and approaches used to simulate the hot-electron effect, oxide time-dependent breakdown, electromigration, and bipolar transistor gain degradation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hot-electron-induced degradation and post-stress recovery of bipolar transistor gain and noise characteristics

Hot-carrier-induced degradation and post-stress recovery of bipolar transistor gain and low-frequency noise are investigated. Forward-bias recovery allows a partial reversal of degradation, and is believed to be due primarily to a reduction of the number of electrons trapped in the oxide. Thermal annealing, which is capable of removing interface states as well, produces a larger recovery of both gain and noise performance measures. >

Suppression of latch in SOI MOSFETs by silicidation of source

It is demonstrated that silicidation of the source region in a silicon-on-insulator MOSFET can improve the parasitic bipolar induced breakdown voltage to beyond 5 V. The technique results in a degradation of the parasitic bipolar current gain by increasing the minority carrier current across the source body junction, thereby causing a reduction in the emitter efficiency. Silicidation of both the source and drain regions is performed simultaneously thus maintaining device symmetry and simplicity of processing. No significant degradation of drain leakage leakage current was observed.

Effects of molybdenum contamination resulting from BF 2 implantation

When molybdenum is utilized for the construction of arc chambers for ion implanters, the species 98Mo 2+ is co-implanted during 11B 19F + 2 implantation, due to its coincident charge-to-mass ratio. The metal ions are generated as the fluorinated species in the source plasma react with the molybdenum arc chamber components. The peak molybdenum concentration in the substrate, as measured by secondary ion mass spectrometry, increases with increasing source arc current for a given dose. Molybdenum acts as a deep-level impurity, which significantly reduces bipolar transistor gain. The diffusion of molybdenum in silicon is studied and its effect on solid state device performance is discussed. Tantalum is suggested as an alternative source material.

The impact of trench isolation on latch-up immunity in bulk nonepitaxial CMOS

Numerical simulations have been used to show that two-dimensional effects can improve the latch-up immunity of deep trench-isolated, bulk, nonepitaxial CMOS. It is observed that the holding voltage is strongly influenced by trench dimensions and layout, which affect the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions, which also changes the parasitic bipolar current gain. To increase the holding voltage, design parameters that are unique to deep trench isolation have been identified. The theoretical understanding that has been obtained can be exploited to design latch-up-free submicrometer CMOS at high packing densities without using expensive epitaxial substrates. >

Characterization of polycrystalline silicon–single-crystal silicon interfaces and correlation to bipolar transistor device data

Depth-resolved secondary-ion mass spectrometry (SIMS) and high-resolution transmission electron microscopy were used to study the composition and structure of the arsenic-doped polycrystalline silicon (polysilicon)–single-crystal silicon interface. This interface remains intact during an 880 °C anneal, with no alignment of the polysilicon occurring. When the interfacial oxide varies from a thin, discontinuous film, to a continuous layer, SIMS analysis is able to quantify differences in the interfacial oxygen content. This interfacial oxygen, expressed as oxygen atoms/cm2, is found to correlate to polysilicon emitter bipolar transistor device current gain.

Experimental and simulation study of the effects of cosmic particles on CMOS/SOS RAMs

The existence of a charge multiplication effect in CMOS/SOS RAM circuits, as reported by J. Rollins (1987), is confirmed. Shorter channel lengths and higher power supply voltages caused the ratio, M, of upset charge to deposited charge to increase. As a result of this multiplication factor, actual devices are more likely to upset than expected from an analysis of only the collected charge. A mixed-mode simulator was used to model the charge collection process. The results showed that the M factor is a very fluid number which is dependent on minority carrier lifetime, drain voltage, and the switching dynamics of the cell in addition to the dependence on mobility ratio and channel length reported by Rollins. Parasitic bipolar gain at high injection levels appears to be the primary mechanism allowing collected charge to be greater than deposited charge. The simulator and experimental data show that, as floating body static memory transistors are down scaled, the particle energy needed to upset the cell is reduced because of the enhanced parasitic bipolar gain effect as well as a reduction in the node capacitance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Model for CMOS/SOI single-event vulnerability

A lumped-parameter model derived from transistor characterization data has been used in SPICE analyses to study and predict the single-event-upset thresholds for SIMOX SOI (separation by implantation of oxygen, silicon-on-insulator) SRAMs (static random-access memories) with a variety of cell designs. The modeling of CMOS/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure. Results indicate that, in the SOI devices investigated, single events simulate a localized bipolar response, even in devices with bodies electrically tied to active nodes. The bipolar response enhances the destabilizing effect of an ion event. The total current impulse contributing to upset can be significantly greater than that produced by direct ionization within the hit transistor, i.e., devices can be upset by ions that deposit less than the total charge required to initiate logic state reversal. In light of this, advanced CMOS/SOI-SOS logic with short channel lengths (and therefore significant parasitic bipolar gain) may exhibit critical LETs (linear energy transfers) lower than expected from simple scaling rules, and thinning of the active regions may not significantly reduce single-event rates in such CMOS/SOI digital circuits. >

N-channel MOSFET breakdown characteristics and modeling for p-well technologies

A model of n-channel MOSFET breakdown, in a p-well, is proposed based on experimental measurements. The model identifies three parasitic bipolar transistors that generate two independent breakdown paths. The breakdown path is dependent on the biasing conditions, the relative parasitic bipolar transistor gain, and the drain avalanche breakdown. Typical biasing of the n-channel MOSFET will result in a breakdown path, and hence snapback sustaining voltage, which is a function of the gate length. While this result is similar to that found in previous studies of snapback on bulk substrates, there is an additional component of current present at the source due to the parasitic vertical bipolar transistor created by the p-well. Another separate parasitic vertical bipolar transistor can lead to an alternative breakdown path when the n-substrate is grounded or left floating. This alternative breakdown path is independent of the gate length for long channel lengths and dependent for short channel lengths. Experimental data and characterization results are presented from two Harris 5-V CMOS processes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Platinum silicide shallow contacts for CMOS integrated circuits

P-channel MOS transistors have been fabricated with Schottky barrier source and drain regions. Shallow BF 2 ion implanted surface layers were used to lower the platinum silicide source to inverted channel barrier height and full current drive was obtained. Bipolar transistors with such Schottky emitters resulted in greatly reduced current gain compared to diffused emitters. Thus this modified Schottky junction p-channel MOS transistor can find application in CMOS, thereby lowering the parasitic bipolar current gain product without sacrificing MOS current drive. This structure, therefore, offers increased protection against latch-up.

Quadruple-well CMOS for VLSI technology

A novel process has been developed to fabricate high-density CMOS with four wells. These wells are self aligned to increase packing density. Two of them are relatively deep wells used to optimize both n- and p-channel active devices. The other two are shallow wells under field oxide to form channel stops for both device types. The channel stops provide rigorous isolation among similar devices and between the devices of the opposite polarity. Subthreshold leakage currents in isolation regions are <0.05 pA/µm when devices are biased at <16.5 V. The channel stops also suppress lateral parasitic bipolar action. To reduce the vertical bipolar gain, a new process technique employing a double-retrograde well and transient annealing has been established. For the CMOS structure with 2-µm p+-to-p-well spacing, we have eliminated latchup by suppressing the beta product to below unity. Moreover, the quadruple-well approach has produced active n- and p-channel FET's with excellent characteristics such as low threshold voltage (∼±0.5 V), low subthreshold slope (≲95 mV/dec), low contact resistivity (∼10-7Ω-cm2), and high channel mobility (620 and 210 cm2/V . s).

Effect of silicide process on bipolar transistor current gain

Emitter Gummel number of modern bipolar transistors is an important factor in determining device performance, especially for heavily doped, shallow junction transistors. Removal of even small amounts of the active dopant from the shallow emitter, e.g., Ar sputteretch and PtSi formation, can significantly reduce the current gain of bipolar transistors. A simple theory of bipolar transistor gain shows that degradation of current gain is due to the reduction of emitter Gummel number. Emphasis is placed on the control of the Ar sputteretch and PtSi formation to obtain desired current gain and to determine its implication in the development of advanced bipolar transistors with very shallow emitter junctions.

Electrical properties of silicon-implanted furnace-annealed silicon-on-sapphire devices

The crystalline quality of s.o.s. layers can be improved near the silicon-sapphire interface by silicon implantation followed by recrystallisation. Device performance on such layers is markedly improved as to n-channel m.o.s.t. noise and leakage current, reverse diode current and lateral bipolar transistor gain. Minority-carrier lifetimes up to 50 ns are deduced.

Combined Neutron and Thermal Effects on Bipolar Transistor Gain

An approximate model has been developed to extend room temperature neutron transistor gain characterizations to temperature extremes. The model can extrapolate transistor gain specifications without recharacterizing device types for temperature or neutron effects. The simplified model can be inaccurate at low currents and for those transistors where the surface effects are significant. However, the model shows good agreement with experiment over two orders of magnitude in operating current level and can be used as a valuable design/analysis tool. Comparison of neutron degradation data (at room temperature) with the prediction based on transistor gain bandwidth product (fT) can be used to estimate the significance of surface effects.