Binary Content Addressable Memory Research Articles

Ferroelectric Field Effect Transistors–Based Content‐Addressable Storage‐Class Memory: A Study on the Impact of Device Variation and High‐Temperature Compatibility

Hafnium oxide (HfO2)‐based ferroelectric field effect transistors (FeFETs) revolutionize the emerging nonvolatile memory area, especially with the potential to replace flash memories for several applications. In this article, the suitability of FeFET memories is investigated, especially FeFET‐based content addressable memory (CAM) cells, as storage‐class memory under junction temperature variations. FeFETs with silicon oxynitride interfacial layer are fabricated and characterized at various temperatures, varying from room temperature to 120 °C. Although the memory window, numbers of programmable states, and endurance deteriorate at high temperatures, FeFETs show excellent robustness in data retention, write latency, and read stability at all temperatures, especially for binary operation. Finally, system‐level simulations using a Simulation Program with Integrated Circuit Emphasis software using experimental data are conducted to gauge the robustness of the data‐search operation using the CAM array under different temperatures. Despite temperature‐variation‐induced changes in FeFET devices, it is observed that binary CAM cells perform robust and unerring search operations for storing and searching data at temperatures up to 120 °C.

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices

This study proposes a self-rectifying ferroelectric tunnel junction (SR-FTJ) crosspoint array to satisfy the stringent size requirements of the Internet-of-Things devices. Each cell in the SR-FTJ crosspoint array consists of two SR-FTJs stacked vertically, resulting in ultrahigh density. The SR-FTJ crosspoint array can operate as: 1) ternary content-addressable memory (TCAM) or 2) binary content addressable memory (BCAM) or physically unclonable function (PUF) in the dual-mode operation. In the dual-mode operation, the amount of the current flowing through the SR-FTJs remains the same, resulting in a stable PUF response regardless of the BCAM data. The dual-mode operation of the SR-FTJ crosspoint array is experimentally verified by 4-in wafer-level demonstrations. HSPICE simulation results using the industrial-compatible 180-nm technology with the SR-FTJ model reflecting measured characteristics show that the SR-FTJ crosspoint array achieves the lowest search energy (2.05 fJ/search/bit) and the highest randomness (Hamming weight of 0.5000) among the previous content addressable memories (CAMs) and PUFs. In addition, the SR-FTJ crosspoint array reduces area by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 84.2% compared to the previous structures that implement individual CAM and PUF.

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory

This work presents BP-SCIM: a reconfigurable 8T static random access memory (SRAM) macro for bit-parallel searching and computing in-memory (CIM). The decoupled read/write ports of the employed 8T SRAM bit-cell eliminate read disturbance during search and CIM operations. BP-SCIM can support both in-memory Boolean logic and arithmetic operations. Novel CIM-friendly algorithms and peripheral circuits are proposed to reduce the latency of complex arithmetic operations such as multiplication and division. In addition, BP-SCIM can be configured as either a binary content-addressable memory (CAM) or a ternary CAM for fast searching. A 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 64 BP-SCIM test chip was implemented in 65-nm CMOS technology. The 8-bit addition and 8-bit multiplication operations can achieve the maximum energy efficiency of 3.11 TOPS/W and 0.17 TOPS/W, respectively at 0.7 V supply. For the binary CAM search operation, BP-SCIM can achieve the minimum energy consumption of 0.91 fJ/bit/search at 87 MHz and 0.8 V supply.

A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM

his work gives a comparison between two approaches used for improving search operation speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a parallel type of computer memory that quickly searches for and retrieves specific data stored within the memory by assigning a unique address to each piece of data. This hardware-based technique is more efficient than traditional software-based techniques such as Linear, Binary, and hash-based. The FPGA-based BiCAM is implemented using two different approaches: using Flip-flops and Block Random Access Memory as the memory element. The performance of these implementations is evaluated through Time complexity analysis, resource utilization, and search speed. The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach. With the current increasing demand for faster and more efficient search operations, this approach can play an important role in optimizing search operations.

An Ultracompact Single‐Ferroelectric Field‐Effect Transistor Binary and Multibit Associative Search Engine

Content addressable memory (CAM) is widely used in associative search tasks due to its parallel pattern matching capability. As more complex and data‐intensive tasks emerge, it is becoming increasingly important to enhance CAM density for improved performance and better area efficiency. To reduce the area overheads, various nonvolatile memory (NVM) devices, such as ferroelectric field‐effect transistors (FeFETs), are used in CAM design. Herein, a novel ultracompact 1FeFET CAM design that enables parallel associative search and in‐memory hamming distance calculation is used, as well as a multibit CAM for exact search using the same CAM cell. The proposed CAM design leverages the 1FeFET1R structure, and compact device designs that integrate the series resistor current limiter into the intrinsic FeFET structure are demonstrated to turn the 1FeFET1R structure into an effective 1FeFET cell. A two‐step search operation of the proposed binary and multibit 1FeFET CAM array through both experiments and simulations is proposed, showing a sufficient sensing margin despite unoptimized FeFET device variation. In genome pattern matching applications, using the hyperdimensional computing paradigm, the design results in a 89.9× speedup and 66.5× improvement in energy efficiency over the state‐of‐the‐art alignment tools on GPU.

BiCAM-based automated scoring system for digital logic circuit diagrams

Abstract In online education, it is critical for the quality of education to evaluate and grade the assignments or examinations that students upload to the system. However, it is time-consuming to determine how well the circuit drawings prepared for the digital logic course, which is a fundamental course in computer engineering and similar disciplines, are not only correct but also compatible with the truth table. Content-addressable memory (CAM), also known as associative memory, is a data storage and retrieval unit. Typically, it is used instead of the conventional memories in fast-paced and time-sensitive applications such as address lookup in Internet routers, databases, and pattern recognition. CAMs implement the search process by comparing the content itself with a key instead of finding the address like the conventional memories. To see the effect of using binary content-addressable memory-based memory on the time spent scoring hand or digital-drawn logic circuits, it is compared with various data structures commonly used in logic simulation programs. I found a significant relationship (O(1)), indicating that the proposed architecture reduces the time complexity in the search process. This expression is the same as time complexity in hash tables.

Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture

The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and 10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which affect the reliability of In-Memory Boolean Computation (IMBC) operations. To overcome these problems, local bit-line Shared pass-gate Dual-Port 8T (SDP8T) SRAM-based IMC architecture is proposed to perform energy-efficient IMBC operations. The local bit-line shared pass-gate structure addresses the half select issues with a small area overhead and achieves higher array efficiency by incorporating the bit-interleave architecture. The virtual-VSS write-assist is used in SDP8T SRAM to improve the write-margin yield (μ−3σ) by 48.99%, and multi-VTH technique improves Decoupled Read-Margin (DRM) yield by 5.26% when compared to DP8T SRAM. The Dynamical Reset Word Line (DRWL) scheme is proposed to resolve the sneak current problem and make the proposed IMC architecture more resilient to compute disturbance at non-read decouple paths during IMBC operations. Further, the Reference-based Reconfigurable Sense Amplifier (RRCSA) scheme is proposed to achieve reliable (compute-failure free) sensing for IMBC on four operands simultaneously in a single cycle, normal read, and Binary Content Addressable Memory (BCAM) operations. The 4 Kb SRAM array is implemented in 65-nm CMOS technology to analyze the SDP8T-IMC architecture. The operating frequency of 1190 MHz and average-energy consumption of 18.56 fJ/bit are achieved during IMBC operation at 1V. For BCAM operations, it achieves 0.60 fJ/search/bit energy consumption in the worst case (i.e., all data mismatch) at 1V. Cumulatively, the proposed SDP8T-IMC architecture has the highest figure of merits than the recently reported IMC architecture.

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed and high density; however, such implementations require the use of system clocks, and thus, suffer from timing violations and design limitations, such as charge sharing. In this paper, we propose a static-based architecture for a low-power, high-speed binary CAM (BCAM) and ternary CAM (TCAM), using a nanoelectromechanical (NEM) memory switch for nonvolatile data storage. We designed the proposed CAM architectures on a 65 nm process node with a 1.2 V operating voltage. The results of the layout simulation show that the proposed design has up to 23% less propagation delay, three times less matching power, and 9.4 times less area than a conventional design.

Design and Implementation of Gray-Coded Bit-Plane Based Reconfigurable Motion Estimation Architecture Using Binary Content Addressable Memory for Video Encoder

Motion Estimation (ME) is the most power consuming module in the video encoder due to its high computational complex operations. So designing an efficient ME hardware without losing coding performance is a major challenge. This paper proposes a low-bit-depth ME technique based on Gray-Coded bit-planes and its hardware implementation using Binary Content Addressable Memory (BCAM). The proposed method significantly reduces the computational burden due to its low-bit-depth representation. The novel BCAM based ME hardware provides faster results because of its on-chip memory computation without compromising other performance parameters. It can process 8K @53.71 fps operated at maximum frequency of 155 MHz with 152.78K NAND equivalent gate count using 90 nm technology library.

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

In-memory computing establishes a new and promising computing paradigm aimed at solving problems caused by the von Neumann bottleneck. It eliminates the need for frequent data transfer between the memory and processing modules and enables the parallel activation of multiple lines. However, vertical data storage is generally required, increasing the implementation complexity for the SRAM writing mode. This article proposes a 10-transistor (10T) SRAM to omit vertical data storage and improve the stability of in-memory computing. A cross-layout of the word line enables arrays with multirow or multicolumn parallel activation to perform vector logic operations in two directions. In addition, the novel horizontal read channel allows matrix transposition. By reconfiguring the data lines, sense amplifiers, and multiplexing read ports, the proposed SRAM can be regarded as a content-addressable memory (CAM), and its symmetry provides selectable data search by column or by row according to the application that easily fits the SRAM storage mode without additional data adjustments. A proposed self-termination structure aims to decrease search energy consumption by approximately 38.5% at 0.9 V at the TT process corner. To verify the effectiveness of the proposed design, a 4 Kb SRAM was implemented in 28-nm CMOS technology. The read margin of the proposed 10T SRAM cell is three times higher than that of the conventional 6-transistor cell. At 0.9 V, logic operations can be performed at approximately 300 MHz, and binary CAM search operations are achieved at approximately 260 MHz with around 1 fJ of energy consumption per search/bit.

Nanoelectromechanical-Switch-Based Binary Content-Addressable Memory (NEMBCAM)

This paper proposes a novel nanoelectromechanical-switch-based binary content-addressable memory (NEMBCAM) for the first time. A nanoelectromechanical (NEM) memory switch serves as both a nonvolatile memory and a switchable current path in an NEMBCAM unit cell. Owing to monolithic three-dimensional integration, NEMBCAM achieves a smaller unit cell area in comparison with conventional complementary metal–oxide–semiconductor-only binary content-addressable memory. Small unit cell area results in reduced match line (ML) capacitance, which lowers search energy consumption. Furthermore, a shorter search delay is achieved owing to the near-perfect on/off characteristic of the NEM memory switch.

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

The von Neumann architecture is approaching its limits in terms of scalability and power consumption. In-memory computation is a possible approach to mitigate this limitation. This brief proposes a configurable 8T static random access memory (SRAM) cell with double word lines and three read ports for in-memory computing. In addition to the normal SRAM function, XOR/XNOR and compound Boolean logic operations of three or four operands, such as AND-OR, AND-OR-INVERT, OR-AND, and OR-AND-INVERT, can be performed in one cycle by fully utilizing the three read ports to obtain 13.2-fJ/bit consumption at 0.6 V. The logic operation frequency is 793 MHz at 1.2 V. The proposed SRAM effectively resolves the bottleneck of the existing in-memory computation schemes that only support compound Boolean logic operations with more than two cycles. In addition, the proposed SRAM array scheme can be configured and used as a binary content-addressable memory or a ternary content-addressable memory for searching operations; it achieves 0.24 fJ/search/bit at 0.6 V in the worst case. At 1.2 V, the searching frequency is up to 813 MHz when searching 128 bits with 65-nm technology.

Design and Performance Analysis of Low Power High Speed CNTFET Binary Content Addressable Memory Cell for Next Generation Communication Networks

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) cells are proposed. The adiabatic logic is integrated with the proposed BCAM cells to improve performance. The performance of proposed BCAM cells is presented for various CNTFET parameters such as number of tubes, chirality vector, pitch value, dielectric constant and dielectric materials. It also explores the optimum set of CNTFET parameters for low power and high speed characteristics of the proposed BCAM cells. Simulation results show an improvement in the average power and delay of proposed BCAM cells. The average power of the proposed BCAM cells is in the order of nano watts while the CMOS based BCAM cells is in the order of micro watts. The delay of the proposed BCAM cells is improved by 56.4 %. All simulations are conducted for both CMOS and CNTFET based BCAM cells in HSPICE at 32 nm technology.

Design of Low Power and High Speed Decoder and Priority Encoder using Carbon Nanotube Field Effect Transistor for Binary Content Addressable Memory Array

In this paper, design of Positive Feedback Adiabatic Logic (PFAL) based decoder and priority encoder using Carbon Nanotube Field Effect Transistor (CNTFET) for Binary Content Addressable Memory (BCAM) array is presented. The optimum set of CNTFET parameters such as number of tubes, chirality vector, pitch, dielectric constant and dielectric materials for low power and high speed encoder and decoder is used. The performance of proposed decoder and priority encoder is analyzed for average power, peak power and delay. Simulation results show that the proposed circuits outperforms compared to that of CMOS technology based circuits. The average power and peak power of the proposed decoder and priority encoder are in the range of μW while the range of values for CMOS based decoder are mW. The average delay of the proposed decoder is improved by 35.96% compared to that of CMOS based decoder. The average delay of the proposed priority encoder is improved by 30.77% compared to that of CMOS based priority encoder. All simulations are conducted for both CMOS and CNTFET based decoder and Priority encoder in HSPICE at 32 nm technology.

Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4x4 CNTFET BCAM array are in the range of micro watt (μW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.

PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration

Modern field-programmable gate arrays (FPGAs) provide a vast amount of logic resources that can be used to implement complex systems while providing the flexibility to modify the design once deployed. This makes them attractive for software-defined networks (SDNs) applications, and, in fact, most vendors provide the building blocks needed for those applications, which include basic packet classification functions such as exact match, longest prefix match, and match with wildcards. Those are needed for different functions such as routing, security filtering, monitoring or quality of service. The match with wildcards can be done using ternary content addressable memories (TCAMs). TCAMs can be implemented as independent standalone devices or as Internet Protocol (IP) blocks that are used inside networking application-specific integrated circuits (ASICs) such as switching ICs. In both cases, the cells of a TCAM are more complex than that of a normal memory and also than that of a binary content addressable memory (CAMs). This is due to the more complex matching that they need to implement. As FPGAs are used in many different applications, it does not make sense to include TCAM blocks inside them as they would be used only in a small fraction of the systems. Therefore, TCAMs are emulated using the logic resources available inside the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed, some of them based on the use of the logic resources and others on the use of the embedded memory blocks available on the FPGA. In this brief, a technique to efficiently emulate TCAMs on Xilinx FPGAs is presented. The proposed scheme is based on the use of lookup tables (LUTs) and partial reconfiguration to achieve a more effective use of the FPGA resources while supporting the addition and removal of rules. The proposed scheme has been compared to existing implementations and the results show that it can achieve significant savings in resource usage. In addition, it enables the use of all the LUTs in the device for TCAM implementation, something that is not supported by existing approaches that use LUTRAMs.

Low Power High Speed Ternary Content Addressable Memory

Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.

Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V $V_{\mathrm {DDmin}}$

This paper presents a 4+2T SRAM for embedded searching and in-memory-computing applications. The proposed SRAM cell uses the n-well as the write wordline to perform write operations and eliminate the write access transistors, achieving 15% area saving compared with conventional 8T SRAM. The decoupled differential read paths significantly improve read noise margin, and therefore reliable multi-word activation can be enabled to perform in-memory Boolean logic functions. Reconfigurable differential sense amplifiers are employed to realize fast normal read or multi-functional logic operations. Moreover, the proposed 4 + 2T SRAM can be reconfigured as binary content-addressable memory (BCAM) or ternary content-addressable memory (TCAM) for searching operations, achieving 0.13 fJ/search/bit at 0.35 V. The chip is fabricated in 55-nm deeply depleted channel technology. The area efficiency is 65% for a $128 \times 128$ pushed-rule array including all peripherals such as column-wise sense amplifier for read/logic and row-wise sense amplifier for BCAM/TCAM operations. Forty dies across five wafers in different corners are measured, showing a worst-case read/write $V_{\mathrm {DDmin}}$ of 0.3 V.

Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells

This paper presents the design and the analysis of power efficient binary content addressable memory (PEBCAM) core cells using the energy recovery principle of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is built by using a basic CAM cell, but the peripheral circuits are realized by using different adiabatic logic structures. In this paper, we propose the design of 3 novel power efficient binary content addressable memory core cells (PEBCAM core cells) using adiabatic logic, namely improved efficient charge recovery logic (IECRL) CAM core cell, positive feedback adiabatic logic (PFAL) CAM core cell and pass transistor adiabatic logic (PAL) CAM core cell. Memory arrays of size 4 $$\times $$? 4 were designed and implemented using the proposed PEBCAM core cells in 45nm CMOS technology. It was found that recovery of dissipated power using adiabatic logic was better than the other CAM structures. The simulation results of the PEBCAM-IECRL CAM proved to be better with a power saving of 77.8% than the conventional adiabatic CAM structures. The circuits were designed using 45nm CMOS technology with a sinusoidal power clock of 1 V and other node voltages at 0.7 V using Cadence Virtuoso.