Bias Temperature Instability Research Articles

Impact of negative bias temperature instability on single event transients in scaled logic circuits

AbstractAltering the performance of single transistors and integrated circuits at nominal operating conditions over time, as well as soft errors, are serious reliability issues for integrated CMOS circuits, especially when used in space applications. In principle, the effect of soft errors becomes even more critical if the circuit performance degrades over time. To address this detrimental behavior, the impact of performance degradation due to NBTI on the soft error susceptibility of integrated circuits is analyzed thoroughly. For this, we analyze the critical charge sensitivity of the two‐input NAND gate and NOR gate for different operating temperatures at stress times up to 3 years. The results show that the critical charge decreases with the temperature and strongly depends on the input states. Next, we validate the results employing the c17 ISCAS'85 benchmark suite, employing the PTM model with the HSPICE to estimate the soft error at the sensitive nodes. The critical charge is observed to be sensitive to the selected supply voltage and device temperature and thus provides a good measure for the soft error susceptibility with respect to NBTI at various operation conditions.

Reliability of p-GaN Gate HEMTs in Reverse Conduction

Synchronous buck converter comprises a low side (LS) and a high side (HS) switch, where the HS switch works in the first quadrant (forward conduction) whereas the LS switch works in the third quadrant (reverse conduction). However, the reliability of the p-GaN gate high electron mobility transistor (HEMT) in reverse conduction is unclear. In this work, a comprehensive evaluation of this conduction mode for 200-V HEMTs was conducted. First, devices were subjected to time-dependent breakdown (TDB) measurements. By comparing different device configurations, the time to failure (TTF) was found to only scale with the number of gate fingers instead of the gate width ${W}_{G}$ , proving the critical spots are the intersection of gate fingers over the N implantation isolation. The reverse operation voltage of ${V}_{DS}$ for ten years lifetime was extrapolated to be −5.4 V, corresponding to a failure of 0.01% and 100 gate fingers. Second, the devices were submitted to 200-V ${V}_{DS}$ OFF-state stress for 10 s, after which the reverse drain current saw a negligible degradation. Third, the reverse conduction of the HEMTs only showed a very limited deterioration after a long-time bias temperature instability (BTI) stress at ${V}_{DS} = - 5.5$ V and ${V}_{GS} = 0$ V. This work proves the p-GaN gate HEMTs bear a high reliability in reverse conduction, which can simplify the design of synchronous power system.

A statistical study into reliability of FPGA implemented circuits: Simulation and modelling

In this work, we report on the development of a methodology to study the reliability of digital circuits implemented in FPGA. For this, the design and simulation tools have been extended to introduce aging. The aging laws for Look-Up Tables, describing the drifts in the propagation time, caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms, have been integrated into the simulation environment by introducing additional variables and equations. Moreover, the study has been further extended by considering the statistical dispersion in the failure time due to different sources of dispersion. Furthermore, an analytical and a statistical model of the failure time of the digital circuit as a function of the clock frequency, aging law parameters and dispersion parameters have been proposed. Finally, the developed methodology has been applied to two different digital circuits implemented in FPGA.

Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits

Bias Temperature Instability and soft error rate are the major reliability issue with the technology scaling. BTI leads to an increase in the threshold voltage of the MOS transistors, which reduces the drain current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this paper, we propose a novel reliable voltage bootstrapped Schmitt trigger circuit with soft error hardening enhancement and lower effect of BTI. We investigate all the circuit simulations which impact on the soft error rate of inverter circuits using HSPICE 65 nm CMOS technology. The results show that the proposed inverter circuit has a higher critical charge and lower soft error rate (SER) when compared to other reference inverter circuits. To better assess, we introduced Vth sensitivity and observed that the degradation of the proposed inverter circuit is 30% higher as compared to conventional CMOS inverter. The proposed inverter offers lower dynamic power, leakage power, and circuit delay of 91.11%, 93.47%, and 38.17%, respectively, as compared to CMOS inverter at 3 years of the stress time. Finally, the overall circuit performance is evaluated using the figure of merits and observes that the proposed inverter has the highest FOM correspond to other inverter circuits, which reveal that the proposed circuit is useful for the applications where the effect of radiations are higher.

A Physical Model for Bulk Gate Insulator Trap Generation During Bias-Temperature Stress in Differently Processed p-Channel FETs

A deterministic reaction-diffusion–drift model is used for the time kinetics of bulk gate insulator trap generation in p-channel Field Effect Transistors (FETs) under inversion stress. The consistency of the deterministic and stochastic versions of the model is shown. The model is independently validated using stress-induced leakage current data from various reports. The model is incorporated into the already existing bias temperature instability (BTI) analysis tool framework and validated using negative BTI data. The measured data from FinFETs having different channel material, substrate type, gate insulator process, and fin length, as well as gate-all-around stacked nano sheet (GAA-SNS) FETs are modeled.

Influence of Buried Oxide Si+ Implantation on TID and NBTI Effects for PDSOI MOSFETs

The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

An Automated Setup for the Characterization of Time-Based Degradation Effects Including the Process Variability in 40-nm CMOS Transistors

This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly.

Bias Temperature Instability of Silicon Carbide Power MOSFET under AC Gate Stresses

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off -state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off -state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications.

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent $n$ from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.

A Comparative Study of AC Positive Bias Temperature Instability of Germanium nMOSFETs With GeO₂/Ge and Si-cap/Ge Gate Stack

AC positive bias temperature instability (PBTI) of germanium nMOSFETs with GeO2/Ge and Si-cap/Ge gate stack was investigated in this brief. AC-DC-AC alternating PBTI stress tests were conducted on both types of devices, the experiment data shows the inserted DC stress phase has little impact on the following AC stress kinetics on GeO2/Ge nMOSFETs but introduce a significant “additional DC generation” on Si-cap/Ge devices. The “additional DC generation” is ascribed to the existence of energy alternating defects (EAD) according to previous studies. Energy distribution under DC and AC stress further demonstrate that EAD are significant on Si-cap/Ge but negligible on GeO2/Ge devices. Effective lifetime prediction is carried out and compared under DC stress after discharge (with a purposely introduced measurement delay) and AC stress on both GeO2/Ge and Si-cap nMOSFETs. The results show GeO2/Ge nMOSFETs’ effective lifetime exhibits no difference under two stress modes, while Si-cap/Ge nMOSFETs’ effective lifetime is underestimated using DC stress after discharge approximation without considering the EAD-induced “additional DC generation”. An extra 0.14V 10-year Vdd design margin can be obtained for Si-cap/Ge nMOSFETs to gain higher performance by taking “additional DC generation” into account. The conclusion is beneficial for process optimization and PBTI reliability improvement of Ge nMOSFETs.

Data-Driven Modeling of Low Frequency Noise Using Capture-Emission Energy Maps

A new approach for modeling low frequency noise is presented to enable the predictions of noise behavior from negative bias temperature instability (NBTI). The noise model is based on a capture-emission energy (CEE) map describing the probability density function of widely distributed defect capture-emission activation energies. To enlarge the capture-emission energy window and to perform the accurate estimation of the recoverable component of CEE, the Gaussian mixture model (GMM) is applied to the CEE map. This approach provides an efficient identification of noise sources and an in-depth noise analysis under both stationary and cyclo-stationary conditions.

Aging in CMOS RF Linear Power Amplifiers: An Experimental Study

An extensive experimental analysis of the hot carrier injection (HCI) and bias temperature instability (BTI) aging effects on RF linear power amplifiers (PAs) is presented in this article. Two different 2.45-GHz PA topologies have been implemented in a CMOS 65-nm technology: one based on a classical common-source (CS) and choke inductor and another one based on a complementary current-reuse (CR) circuit, both of them producing similar gain and output 1-dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1dB</sub> ). These circuits have been stressed to produce accelerated aging degradation, by applying increasing supply (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) voltages or increasing RF input powers (PIN). The degradation on the transistor parameters (threshold voltage and mobility), dc bias point (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> current), and RF performance (gain, matching, and compression point) has been simultaneously measured. This has allowed us to observe how the reduced transistor degradation in CR PA results in higher robustness in its RF parameters compared with the CS PA circuit. The equivalent root-mean-square (rms) voltages have been proposed as an observable metric to assess the combined dc + RF stress in a PA circuit. This has been applied to a semianalytical model, providing comprehension of the link between the conditions under which a circuit is operated, the degradation of the transistor parameters, and the effects on the dc current and RF performance.

Current Understanding of Bias-Temperature Instabilities in GaN MIS Transistors for Power Switching Applications

GaN-based high-electron mobility transistors (HEMTs) have brought unprecedented performance in terms of power, frequency, and efficiency. Application of metal-insulator-semiconductor (MIS) gate structure has enabled further development of these devices by improving the gate leakage characteristics, gate controllability, and stability, and offered several approaches to achieve E-mode operation desired for switching devices. Yet, bias-temperature instabilities (BTI) in GaN MIS transistors represent one of the major concerns. This paper reviews BTI in D- and E-mode GaN MISHEMTs and fully recess-gate E-mode devices (MISFETs). Special attention is given to discussion of existing models describing the defects distribution in the GaN-based MIS gate structures as well as related trapping mechanisms responsible for threshold voltage instabilities. Selected technological approaches for improving the dielectric/III-N interfaces and techniques for BTI investigation in GaN MISHEMTs and MISFETs are also outlined.

The analysis of static random access memory stability under the influence of statistical variability and bias temperature instability-induced ageing

In this paper, the stability of static random access memory (SRAM) under the influence of statistical variability and bias temperature instability (BTI) induced ageing is investigated by statistical simulations. Effectively infinite and accurate compact models are successfully generated using ModelGenTM technology to prevent subsampling problem and ensure the statistical SRAM investigation, which successfully present device simulation results for circuits. The impact of transistor’s statistical variability on the SRAM stability is evaluated by SRAM static noise margin (SNM) sensitivity test. Three BTI induced ageing patterns of the SRAM cell are analysed at different ageing levels. The distribution, increase and decrease percentage of SNM is calculated at statistical level to show the combined effects of transistors’ variability with different ageing pattern.

Non-equilibrium engineering of chemically grown SiO2/Si by UV nanosecond pulsed laser annealing from the viewpoint of bias temperature instability sources

The impacts of high-temperature UV nanosecond pulsed laser annealing (LA) on a chemically grown SiO2/Si system are systematically investigated as a function of the number of irradiated pulses. A progressive transition is observed for both the tetrahedral SiO4 network and the SiO2/Si interface, being assumed to play an essential role in controlling bulk SiO2 traps and interface states. The presented results open the perspective to improve bias temperature instability of low thermal budget gate stacks by UV ns pulsed LA, particularly in emerging 3D integrations.

Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}{)}$ </tex-math></inline-formula> is applied only during ON-state and a constant front-gate stress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> is used, BTI reliability is not influenced by the applied <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> (due to its negligible impact on the front-gate oxide field, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}{)}$ </tex-math></inline-formula> . Therefore, supplying an FBB during ON-state can be used to adjust device performance—as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> modulates the channel current through <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ov}}$ </tex-math></inline-formula> is maintained by adjusting the front-gate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> [i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}{(}{V}_{\text {BG}}{)}$ </tex-math></inline-formula> is kept constant under different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> ’s], the BTI reliability can be improved under FBB (due to a reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}$ </tex-math></inline-formula> in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation.

Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in SiC Power MOSFETs

Junction temperature sensing is an integral part of both online and offline condition monitoring where direct access to the bare die surface is not available. Given a defined power input, the junction temperature enables the estimation of the junction-to-case thermal resistance, which is a key indicator of packaging failure mechanisms like solder voiding and cracks. The use of temperature sensitive electrical parameters (TSEPs) has widely been proposed as a means of junction temperature sensing; however, there are certain challenges regarding their use in SiC MOSFETs. Bias temperature instability (BTI) from charge trapping in the gate dielectric causes threshold voltage drift, which in SiC affects some of the key TSEPs including on -state resistance, body diode forward voltage as well as the current commutation rate. This article reviews the impact of BTI on the accurate junction temperature measurement using TSEPs in SiC MOSFETs.

Time-Dependent Threshold Voltage Instability Mechanisms of p-GaN Gate AlGaN/GaN HEMTs Under High Reverse Bias Conditions

In this article, we experimentally investigate the degradation mechanisms of GaN high-electron mobility transistors (HEMTs) with p-type gate during long-term hightemperature reverse bias (HTRB) stress and negative bias temperature instability (NBTI) stress. Based on a number of stress/recovery experiments, we demonstrate that HTRB stress could lead to hole emission in the p-GaN layer, making threshold voltage (Vth) positively shift, while NBTI stress could result in detrapping at the AlGaN/GaN interface or the AlGaN layer and make Vth negatively shift. It is also found that the temperature rise can suppress the positive Vth shift and accelerate its recovery process in HTRB experiments.

Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (LGs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time to find its suitability in sub-400-mV low-stand-by-power (LSTP) digital operation, followed by finding its reliability and stability against the adverse effect of Positive Bias Temperature Instability (PBTI) for LG = 13 nm corresponding to the (recent) state-of-the-art technology node for the “More Moore” options in realizing LSTP digital functions. The whole work is executed with the help of 2-D numerical methods, via a model-calibration against a couple of experimental works on Elevated-Drain TFET (ED-TFET) and Elevated-Source TFET (ES-TFET), respectively, followed by a comparison of performances between the three, in terms of threshold voltage (VT), average subthreshold swing (SSavg), OFF-state current (IOFF), ION/IOFF ratio, OFF-state leakage power, and drain-induced barrier lowering (DIBL), and then a measurement of shifts in VT, IOFF, ION/IOFF, and SSavg for different PBTI stress conditions for temperature ≥ 300 K. For the optimum value of LG (i.e. 13 nm), a reduction of 56% and 66% in DIBL, a drop of 15.84% and 45.74% in SSavg, a reduction of about 1 decade and 3 decades in IOFF, and an improvement of nearly 1 decade and 2 decades in ION/IOFF have been obtained for the AESD-TFET against the ES- and ED-TFET devices, respectively. The same has also been found to show maximum stability against the PBTI effect under the two-temperature conditions (i.e. 300 K and 398 K) in terms of IOFF, ION/IOFF and SSavg with the lowest possible shifts in VT (∼ 0%) and SSavg (9%), besides maintaining the most excellent absolute values of the aforesaid parameters.

Electrical performances degradations and physics based mechanisms under negative bias temperature instability stress for p-GaN gate high electron mobility transistors

In this paper, an in-depth evaluation of the negative bias temperature instability (NBTI) in p-GaN gate high electron mobility transistors with Schottky-type gate contact has been reported in detail. The measured results reveal that the threshold voltage (V th) positively shifts by 0.35 V and the on-state drain-source resistance (R dson) increases by 24.2 mΩ within 1 h at room temperature, even under the minimum allowed operating gate-voltage condition (V gs = −10 V) in the datasheet of the commercial device. With the help of energy band theory and experimental analyses, donor-type traps are demonstrated to dominate the degradation by reducing the positive charges in the p-GaN cap. Moreover, further quantitative analysis has been performed by the conductance–frequency measurements method. Considering the risk of degradation induced by NBTI, it turns necessary for the system designers to choose a more suitable negative bias operating condition so as to extend the robustness of the entire power system.