Bias Temperature Instability Effect Research Articles

Research on the Coupling Effect of NBTI and TID for FDSOI pMOSFETs.

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips

The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130◦C and T = 25◦C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant.Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130◦C) compared to lower operating temperatures (T = 25◦C).

FinFET-Based Low-Power Improved PDP 4:2 Approximate Compressor Design

In the era of low-power very large-scale integration design, approximate computing is a soaring design paradigm that assures energy-efficient circuit design at the cost of some accuracy. Multiplication is a very important operation of an arithmetic unit and compressor is the inherent part of the multiplier. In this paper, an energy-efficient design of a 4:2 approximate compressor is proposed. The inclusion of the extra leakage control transistors in the logic has led to leakage power reduction, which ultimately reduces the power dissipation in the circuits. The proposed 4:2 compressor is simulated at 10[Formula: see text]nm fin-field effect transistor (FinFET) technology. The proposed compressor has been verified for its functionality and robustness. The proposed design shows a power dissipation of 154.48[Formula: see text]nW and a delay of 9.16[Formula: see text]ps. In comparison to other 4:2 approximate compressors, the proposed compressor shows the least power dissipation, the lowest power delay product (PDP) and the highest robustness. The power dissipation of the proposed compressor is 92.84% less than that of the base compressor. The PDP of the designed compressor is 80.58% less than the minimum PDP among other compressors. The aging analysis for the negative bias temperature instability (NBTI) effect is also checked for the proposed compressor and compared with the existing designs.

An Energy-Efficient Generic Accuracy Configurable Multiplier Based on Block-Level Voltage Overscaling

Voltage Overscaling (VOS) is one of the well-known techniques to increase the energy efficiency of arithmetic units. Also, it can provide significant lifetime improvements, while still meeting the accuracy requirements of inherently error-resilient applications. This paper proposes a generic accuracy-configurable multiplier that employs the VOS at a coarse-grained level (block-level) to reduce the control logic required for applying VOS and its associated overheads, thus enabling a high degree of trade-off between energy consumption and output quality. The proposed configurable Block-Level VOS-based (BL-VOS) multiplier relies on employing VOS in a multiplier composed of smaller blocks, where applying VOS in different blocks results in structures with various output accuracy levels. To evaluate the proposed concept, we implement 8-bit and 16-bit BL-VOS multipliers with various blocks width in a 15-nm FinFET technology. The results show that the proposed multiplier achieves up to 15% lower energy consumption and up to 21% higher output accuracy compared to the state-of-the-art VOS-based multipliers. Also, the effects of Process Variation (PV) and Bias Temperature Instability (BTI) induced delay on the proposed multiplier are investigated. Finally, the effectiveness of the proposed multiplier is studied for two different image processing applications, in terms of quality and energy efficiency.

Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization.

The bias temperature instability (BTI) effect of p-GaN gate high-electron-mobility transistors (HEMTs) is a serious problem for reliability. To uncover the essential cause of this effect, in this paper, we precisely monitored the shifting process of the threshold voltage (VTH) of HEMTs under BTI stress by fast sweeping characterizations. The HEMTs without time-dependent gate breakdown (TDGB) stress featured a high VTH shift of 0.62 V. In contrast, the HEMT that underwent 424 s of TDGB stress clearly saw a limited VTH shift of 0.16 V. The mechanism is that the TDGB stress can induce a Schottky barrier lowering effect on the metal/p-GaN junction, thus boosting the hole injection from the gate metal to the p-GaN layer. This hole injection eventually improves the VTH stability by replenishing the holes lost under BTI stress. It is the first time that we experimentally proved that the BTI effect of p-GaN gate HEMTs was directly dominated by the gate Schottky barrier that impeded the hole supply to the p-GaN layer.

A meta-heuristic search-based input vector control approach to co-optimize NBTI effect, PBTI effect, and leakage power simultaneously

As technology advances, Bias temperature instability (BTI) has become a severe aging challenge that affects the reliability of a device. Previously, NBTI was the most significant aging issue, but with the development of the high-k metal-gate technology, the impact of PBTI can no longer be overlooked. Similarly, in deep submicron technology, leakage power also remains a serious concern. So, minimizing the consequence of the BTI effect and leakage power is the key design goal in today’s technology. As the leakage power and the BTI effects have a strong dependency on the input patterns of the circuit, the input vector control (IVC) technique can be employed to mitigate both of these effects. Previously, IVC techniques have been used to co-optimize the NBTI degradation and the leakage power. In this work, the NBTI effect, PBTI effect, and leakage power are considered simultaneously. Here, a Genetic Algorithm-based (GA) multi-objective meta-heuristic approach is proposed to select the optimum input vector for simultaneous co-optimization of NBTI effect, PBTI effect, and standby leakage power. The proposed approach shows a maximum improvement of NBTI, PBTI, and leakage power by 39.89%, 40.62%, and 37.32%, respectively, with respect to the worst-case solutions of each effect.

Assessment of Negative Bias Temperature Instability Due to Interface and Oxide Trapped Charges in Gate-All-Around TFET Devices

The effects of negative bias temperature instability (NBTI) on emerging tunnel FET (TFET) devices are setting of important reliability concern for analog/digital circuit design. In this work, NBTI effects in gate-all-around tunnel FET (GAA TFET) devices have been thoroughly analyzed and the unstressed p-type GAA TFET transfer characteristics are calibrated with the experimentally published data to tune the models used for the numerical analysis. The GAA device is stressed for different time durations and for different temperatures to analyze the capture and emission probabilities of the trapped charges. The effect of oxide trapping, interface trapping, and trapping of charges at several regions in the channel are analyzed individually, as well as collectively. The sub-threshold voltage of the TFET device is also investigated and it has been found that the change in the sub-threshold slope is not at all degraded by NBTI stress.

Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation

The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads. Finding a feasible worst case workload is difficult due to logical correlation within the logic circuit under consideration. In this article, we propose an NBTI-aware subset simulation (SS) framework that efficiently and accurately finds the failure probability covering various input duty cycles determined by different workloads. In addition, the proposed method is incorporated with the NBTI mitigation technique to facilitate workload-aware mitigation. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to a naive Monte Carlo method. The NBTI mitigation based on SS demonstrates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.78\times $ </tex-math></inline-formula> better mitigation for multiple input duty cycles compared to the conventional method.

An equivalent circuit model of NBTI effect for short-channel P-MOSFET

An equivalent circuit model of the negative bias temperature instability (NBTI) effect in 65 nm P-MOSFET is presented in this paper. Based on an existing P-MOSFET model of a 65 nm CMOS foundry PDK (Process Design Kit) and several basic electrical components and arithmetic cells in the EDA (Electronics Design Automation) library, an equivalent circuit model for NBTI degradation has been achieved. The electrical components and arithmetic cells include voltage source, voltage-controlled voltage source, voltage-controlled current source, adder, and multiplier. The equivalent circuit model includes five tunable input parameters: gate width (W), gate length (L), temperature (temp), stress time (t), and process corner (typical/fast/slow). The model takes into account the effects of drain-source, drain-gate, and gate-source voltage stress states. The effect of process corner on NBTI is also considered. The simulation results show that the performance curve of this P-MOSFET equivalent circuit model is consistent with the measured data in some published literature. This equivalent circuit model can be utilized for long-term reliability IC design.

Ab initio investigations in amorphous silicon dioxide: Proposing a multi-state defect model for electron and hole capture

Experiments as well as theoretical calculations indicate that point defects in the amorphous SiO2 layer of electronic devices as well as in optical fibers are responsible for numerous stability and reliability phenomena, including noise, hysteresis, bias temperature instabilities and decreasing transmission efficiency. In addition to the well-known oxygen vacancy, hydrogen related defects such as the hydrogen bridge and the hydroxyl-E′ center have gained a considerable amount of attention in the recent past, as they are suspected to negatively influence the device performance by capturing charge carriers from e.g. both Si and SiC substrates in field effect transistors. Here, we present a thorough ab initio study of these oxide defects and develop a unified description of electron and hole capture processes in a single multi-state model, supported by a comprehensive analysis of various defect parameters like relaxation energies, charge transition levels, (meta-)stability and transition barriers. We show that a single oxide defect can have two different trap levels for both electron and hole capturing processes, which might be the cause of anomalous device degradation phenomena. Based on its low formation energy compared to other defect types, we find that the hydroxyl-E′ center is the most promising defect candidate to explain charge capture processes in Si/SiO2 systems. Furthermore, we argue that the reduced effect of positive bias temperature instability (PBTI) observed in MOS devices compared to its negative counterpart (NBTI) can be explained by the locations of the hydroxyl-E′ centers charge transition levels.

Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

As CMOS devices become smaller, aging-induced and process variations become major issues for circuit reliability. In this paper, a statistical gate sizing method is proposed to improve the lifetime reliability of manufactured chips in the presence of process variations and aging effects. To this end, we propose a canonical first order delay model to estimate the delay degradation of a gate under negative bias temperature instability and process variations considering spatial correlations. Using the proposed gate delay model, a statistical static timing analysis method is introduced to compute the circuit delay considering the joint effect of process variation and negative bias temperature instability. To guarantee that the circuit meets the required timing constraints, we propose an incremental gate sizing technique. This technique first computes the criticality of each gate defined as the probability that a gate lies on the critical path due to negative bias temperature instability and process variations. Then, a group of gates with the highest ranking according to criticality is chosen for a gate sizing-based timing optimization. It is worth nothing that, by using the proposed statistical gate delay model, we can compute the criticality of each gate incrementally. Experimental results based on ISCAS’85 benchmark circuits show that the proposed method can improve the lifetime reliability defined as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1(\mu + 3\sigma)$ </tex-math></inline-formula> of the initial delay distribution of the circuit at the expense of 8.64% area overhead. In comparison with the path-based method, the proposed approach is much faster, especially for larger circuits, which makes it a viable solution to optimize the lifetime reliability of very large-scale circuits used in industry.

Implication of Self-Heating Effect on Device Reliability Characterization of Multi-Finger n-MOSFETs on 22FDSOI

In this paper, the self-heating effect for multi-finger fully depleted SOI nMOSFETs is investigated. The layout parameters of the transistor are varied, and the conductance-based method is used for the extraction of the thermal resistance. An empirical-based scalable thermal resistance model that accounts for geometrical layout parameters is developed. Further, hot carrier stress degradation is examined, and a correlation between self-heating and hot carrier degradation is established. The associated self-heating with geometrical dimension influences the amount of hot carrier degradation and should be taken into account for accurate degradation modeling. It is found that with the increase of temperature, the contribution of the parasitic bias temperature instability effect increases the drift of the threshold voltage. Improved thermal and reliability performance is achieved for the device structures where a continuous active area is divided into multiple smaller active regions.

Investigation of Negative Bias Temperature Instability Effect in Nano PDSOI PMOSFET.

The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was investigated by accelerated stress tests. The results show that NBTI leads to a threshold voltage negative shift, saturate drain current reduction and transconductance degradation of the PMOSFET. Next, the relationship between the threshold voltage shift and stress time, gate bias and temperature, and the channel length is investigated, and the NBTI lifetime prediction model is established. The results show that the NBTI lifetime of a 130 nm T-Gate PDSOI PMOSFET is approximately 18.7 years under the stress of VG = −1.2 V and T = 125 °C. Finally, the effect of the floating-body effect on NBTI of PDSOI PMOSFET is investigated. It is found that the NBTI degradation of T-Gate SOI devices is greater than that of the floating-body SOI devices, which indicates that the floating-body effect suppresses the NBTI degradation of SOI devices.

Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits

Soft errors, aging effects and process variations have become the three most critical reliabil-ity issues for nanoscale complementary metal oxide semiconductor (CMOS) circuits. In this paper, the effects of bias temperature instability (BTI) and process variations on the threshold voltage of MOS devices are theoretically deduced, and the drift of the threshold voltage under the synergistic effect of BTI and process variations is analyzed. Based on the deduced threshold voltage drift formula under the synergistic effect, the critical charge and delay of different logic gates under different aging times in NanGate&#x2019;s 45 nm process are simulated and analyzed. A method based on the change in the critical charge and delay of the soft error rate (SER) calculation considering BTI effect and process variations is given, and the effective-ness of our method comprehensively demonstrated using the ISCAS85,89 benchmarks. As a result, we can observe that the effect of only considering the BTI effect on the critical charge of the circuit is smaller than that of considering both the BTI effect and process variations. The simulation results show that with in-creasing aging time, the synergistic effect of BTI and process variations makes the increase in the soft error rate more serious than the impact of either effect alone.

Design of low power SRAM- based ubiquitous sensor for wireless body area networks

Purpose Smart ubiquitous sensors have been deployed in wireless body area networks to improve digital health-care services. As the requirement for computing power has drastically increased in recent years, the design of low power static RAM-based ubiquitous sensors is highly required for wireless body area networks. However, SRAM cells are increasingly susceptible to soft errors due to short supply voltage. The main purpose of this paper is to design a low power SRAM- based ubiquitous sensor for healthcare applications. Design/methodology/approach In this work, bias temperature instabilities are identified as significant issues in SRAM design. A level shifter circuit is proposed to get rid of soft errors and bias temperature instability problems. Findings Bias Temperature Instabilities are focused on in recent SRAM design for minimizing degradation. When compared to the existing SRAM design, the proposed FinFET-based SRAM obtains better results in terms of latency, power and static noise margin. Body area networks in biomedical applications demand low power ubiquitous sensors to improve battery life. The proposed low power SRAM-based ubiquitous sensors are found to be suitable for portable health-care devices. Originality/value In wireless body area networks, the design of low power SRAM-based ubiquitous sensors are highly essential. This design is power efficient and it overcomes the effect of bias temperature instability.

Investigating the Current Collapse Mechanisms of p-GaN Gate HEMTs by Different Passivation Dielectrics

In this letter, the dynamic R on degradation mechanisms of the p-GaN gate HEMTs induced by off -state stress are investigated with different passivation dielectrics AlON and SiN. The degradation mechanisms are twofold, including V TH shift and surface trapping in the gate-to-drain access region, whose impacts are successfully distinguished. Surface trapping by SiN passivation is evidently proved to be the dominant factor that can almost induce a full current collapse. The V TH positive shift diminishes the drain current by shrinking the overdrive V GS, which however, can be compensated by a higher V GS overdrive in applications. SiN passivation can effectively suppress the positive bias temperature instability effect, probably by passivating the p-GaN fast traps with hydrogen during passivation. Last, the transient measurements unveil that both the surface trapping and V TH shift have a very slow recovery process.

Influence of Buried Oxide Si+ Implantation on TID and NBTI Effects for PDSOI MOSFETs

The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent $n$ from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.

Asymmetric-Elevated-Source-Drain TFET: A Fairly Scalable and Reliable Device Architecture for Sub-400-mV Low-Stand-by-Power Digital Applications

In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (LGs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time to find its suitability in sub-400-mV low-stand-by-power (LSTP) digital operation, followed by finding its reliability and stability against the adverse effect of Positive Bias Temperature Instability (PBTI) for LG = 13 nm corresponding to the (recent) state-of-the-art technology node for the “More Moore” options in realizing LSTP digital functions. The whole work is executed with the help of 2-D numerical methods, via a model-calibration against a couple of experimental works on Elevated-Drain TFET (ED-TFET) and Elevated-Source TFET (ES-TFET), respectively, followed by a comparison of performances between the three, in terms of threshold voltage (VT), average subthreshold swing (SSavg), OFF-state current (IOFF), ION/IOFF ratio, OFF-state leakage power, and drain-induced barrier lowering (DIBL), and then a measurement of shifts in VT, IOFF, ION/IOFF, and SSavg for different PBTI stress conditions for temperature ≥ 300 K. For the optimum value of LG (i.e. 13 nm), a reduction of 56% and 66% in DIBL, a drop of 15.84% and 45.74% in SSavg, a reduction of about 1 decade and 3 decades in IOFF, and an improvement of nearly 1 decade and 2 decades in ION/IOFF have been obtained for the AESD-TFET against the ES- and ED-TFET devices, respectively. The same has also been found to show maximum stability against the PBTI effect under the two-temperature conditions (i.e. 300 K and 398 K) in terms of IOFF, ION/IOFF and SSavg with the lowest possible shifts in VT (∼ 0%) and SSavg (9%), besides maintaining the most excellent absolute values of the aforesaid parameters.

Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling

Negative Bias Temperature Instability (NBTI) effect occurs in a PMOS transistor when turned ON leading to threshold voltage degradation. As sub-threshold leakage is significant in nanoscale CMOS circuits, input vector control can be employed wherein a Minimum Leakage Vector (MLV) is applied to the circuit during idle periods. In such a case, the ON PMOS transistors on the critical path are subject to NBTI stress for prolonged periods. Transistors can recover from stress when turned OFF. Based on this observation, we propose a vector cycling based leakage/NBTI co-optimization: a pair of MLVs are identified such that when applied alternately, on the critical path, PMOS transistors activated by one vector are turned OFF by the other vector. We employ Simulated Annealing (SA) for stochastic search of the first vector followed by back tracking to identify the second vector. Experimental results for a subset of ISCAS85 benchmarks implemented in 45 nm technology demonstrate the feasibility of vector cycling approach. When compared to leakage-only optimization, NBTI-only optimization, and co-optimization, on average, vector cycling yields 11, 3, and 6 percent NBTI improvements with 18, -9, and 4 percent leakage overheads respectively. The average area and dynamic power overheads are 13.78 and 0.15 percent respectively.