Bias Temperature Instability Effect Research Articles

Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs

The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p-channel metal–oxide–semiconductor field-effect transistor using high-k/metal gate stacks is investigated. The direct current–current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage.

Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip–Flops Under the Negative Bias Temperature Instability Effect

With the CMOS transistors being scaled to 28 nm and lower, negative bias temperature instability (NBTI) has become a major concern due to its impact on pMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of CMOS flip-flops. First, it is shown that the NBTI effect tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing codependent setup and hold time contours of the flip-flops. Third, a multicorner optimization technique, which relies on mathematical programming to find the best transistor sizes, is presented to minimize the energy-delay product of the flip-flops under the NBTI effect. Finally, the proposed optimization technique is applied to true single-phase clock flip-flops to demonstrate its effectiveness.

Effect of Negative Bias Temperature Instability on the Single Event Upset Response of 40 nm Flip-Flops

Negative bias temperature instability has been experimentally demonstrated to increase the cross-section of the single event response for 40 nm flip-flops. Analysis on the underlying mechanisms, including threshold voltage shift, is presented.

Analytical Modeling of Read Margin Probability Distribution Function of Static Random Access Memory Cells in Presence of Process Variations and Negative Bias Temperature Instability Effect

In this work, we present an analytical model for calculating the read margin of static random access memory (SRAM) cells as a function of different transistors parameters. Using this model and assuming normal distribution for the threshold voltages of transistors in the presence of process variations, the probability distribution function (PDF) of the read margin is analytically derived. In addition, the time variation of the PDF due to the negative bias temperature instability (NBTI) effect is also considered in the model. The accuracy of the model is verified by comparing its results with those of HSPICE simulations in 45 and 32 nm technologies. The comparison demonstrates a very high level of accuracy for the proposed model.

Analytical Modeling of Read Margin Probability Distribution Function of Static Random Access Memory Cells in Presence of Process Variations and Negative Bias Temperature Instability Effect

Analytical Modeling of Read Margin Probability Distribution Function of Static Random Access Memory Cells in Presence of Process Variations and Negative Bias Temperature Instability Effect

Design Techniques for NBTI-Tolerant Power-Gating Architectures

While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations impact the lifetime of the overall circuit. pMOS header transistors used in power-gated architectures are one relevant example of such components. For these types of devices, an NBTI-induced current capability degradation translates into a larger -drop effect on the virtual- rail, which unconditionally affects the performance and, thus, the reliability of all power-gated cells. In this brief, we address the problem of designing NBTI-tolerant power-gating architectures. We propose a set of efficient NBTI-aware circuit design solutions, including both static and dynamic strategies, that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads. Experimental results prove the effectiveness of such techniques when applied to a suite of benchmarks mapped onto a 45-nm industrial CMOS technology library. In particular, we prove that it is possible to achieve more than ten times of lifetime extension with respect to a traditional power-gating approach.

Unified Reaction–Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect

In this study, we developed a unified reaction–diffusion (R–D) model for the negative bias temperature instability (NBTI) effect over a wide range of stress times. The newly developed model provides a physics-based uniform solution and overcomes the limitations of the classical R–D models that cannot describe both the short and the long term stress regions simultaneously. In our modeling framework, the chemical reaction between inversion channel carriers and Si–H bonds at the Si/SiO2 interface dominates the short-term NBTI effects at the beginning of the stress application. Then the H2 diffusion into the polycrystalline silicon (poly-Si) gate becomes responsible for long term stress degradation. Finally, the developed R–D model is implemented into the advanced metal oxide semiconductor field effect transistor (MOSFET) model HiSIM to enable accurate circuit-aging simulation. Simulation results for the current degradation and their comparison with measurements verify the achieved high accuracy and the practical applicability of the developed NBTI model.

Unified Reaction–Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect

In this study, we developed a unified reaction–diffusion (R–D) model for the negative bias temperature instability (NBTI) effect over a wide range of stress times. The newly developed model provides a physics-based uniform solution and overcomes the limitations of the classical R–D models that cannot describe both the short and the long term stress regions simultaneously. In our modeling framework, the chemical reaction between inversion channel carriers and Si–H bonds at the Si/SiO2 interface dominates the short-term NBTI effects at the beginning of the stress application. Then the H2 diffusion into the polycrystalline silicon (poly-Si) gate becomes responsible for long term stress degradation. Finally, the developed R–D model is implemented into the advanced metal oxide semiconductor field effect transistor (MOSFET) model HiSIM to enable accurate circuit-aging simulation. Simulation results for the current degradation and their comparison with measurements verify the achieved high accuracy and the practical applicability of the developed NBTI model.

Dependence of the DC stress negative bias temperature instability effect on basic device parameters in pMOSFET

To analyze the dependence of the DC stress negative bias temperature instability (NBTI) effect on basic device paraments, such as the channel length, the gate oxide thickness, the doping concentration, we solve the hydrogen molecule drift-diffusion model of NBTI together with the semiconductor device equations. The results are compared with the existing experimental data and the basic laws and physics of devices, which is necessary for reliability studies of NBTI. The analysis results show that NBTI effect is not affected by the channel length change, but maily by the thickness of the gate oxide layer. Gate oxide thickness thinning and gate oxide layer electric field enhancement effect are consistent, which determines the device degradation in the manner of exponential law. With channel doping concentration increasing, NBTI effect will be reduced, which is because the device channel surface hole concentration is reduced, however with the doping concentration increases to such a value that the device source drain leakage current is very low (low leakage device), the MBTI effect is obviously enhanced. These are helpful for understanding NBTI and designing the high performance device.

Delay sensing for long-term variations and defects monitoring in safety–critical applications

The impact of parametric variations on digital circuit performance is increasing in nanometer Integrated Circuits (IC), namely of Process, power supply Voltage and Temperature (PVT) variations. Moreover, circuit aging also impacts circuit performance, especially due to Negative Bias Temperature Instability (NBTI) effect. A growing number of physical defects manifest themselves as delay faults (at production, or during product lifetime). On-chip, on-line delay monitoring, as a circuit failure prediction technique, can be an attractive solution to guarantee correct operation in safety---critical applications. Safe operation can be monitored, by predictive delay fault detection. A delay monitoring methodology and a novel delay sensor (to be selectively inserted in key locations in the design and to be activated according to user's requirements) is proposed, and a 65 nm design is presented. The proposed sensor is programmable, allowing delay monitoring for a wide range of delay values, and has been optimized to exhibit low sensitivity to PVT and aging-induced variations. Two MOSFET models--BPTM and ST--have been used. As abnormal delays can be monitored, regardless of their origin, both parametric variations and physical defects impact on circuit performance can be identified. Simulation results show that the sensor is effective in identifying such abnormal delays, due to NBTI-induced aging and to resistive open defects.

Negative bias temperature instability induced single event transient pulse narrowing and broadening

The effect of negative bias temperature instability (NBTI) on a single event transient (SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

In this paper, we proposed a new adder design called variable-latency adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of negative bias temperature instability (NBTI) on circuit delay. By applying VL-adder concept to a 64-bit carry-select adder design, more than 40% energy saving is obtained when a similar throughput is maintained.

Study on the negative bias temperature instability effect under dynamic stress

This paper studies negative bias temperature instability (NBTI) under alternant and alternating current (AC) stress. Under alternant stress, the degradation smaller than that of single negative stress is obtained. The smaller degradation is resulted from the recovery of positive stress. There are two reasons for the recovery. One is the passivation of H dangling bonds, and another is the detrapping of charges trapped in the oxide. Under different frequencies of AC stress, the parameters all show regular degradation, and also smaller than that of the direct current stress. The higher the frequency is, the smaller the degradation becomes. As the negative stress time is too small under higher frequency, the deeper defects are hard to be filled in. Therefore, the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.

Performance, reliability, radiation effects, and aging issues in microelectronics – From atomic-scale physics to engineering-level modeling

The development of engineering-level models requires adoption of physical mechanisms that underlie observed phenomena. This paper reviews several cases where parameter-free, atomic-scale, quantum mechanical calculations led to the identification of specific physical mechanisms for phenomena relating to performance, reliability, radiation effects, and aging issues in microelectronics. More specifically, we review recent calculations of electron mobilities that are based on atomic-scale models of the Si–SiO 2 interface and elucidate the origin of strain-induced mobility enhancement. We then review extensive work that highlights the role of hydrogen as the primary agent of reliability phenomena such as negative bias temperature instability (NBTI) and radiation effects, such as enhanced low-dose radiation sensitivity (ELDRS) and dopant deactivation. Finally, we review atomic-scale simulations of recoils induced by energetic ions in Si and SiO 2. The latter provide a natural explanation for single-event gate rupture (SEGR) in terms of defects with energy levels in the SiO 2 band gap.

Competing Degradation Mechanisms in Short-Channel Transistors Under Channel Hot-Carrier Stress at Elevated Temperatures

The temperature dependence of channel hot-carrier (CHC) degradation in n-MOS transistors with high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics has been studied. The analysis starts from the most damaging CHC stress conditions at room temperature ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> /2 for long channels and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> for short channels). We find that, for long-channel transistors, the CHC degradation decreases at high temperature, while for short-channel transistors, an increase is observed. In this paper, a new picture to explain the observed increment of CHC damage with temperature for short-channel transistors with high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric is presented. We demonstrate that the total CHC degradation consists of two components: the classical CHC damage located at the drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered a positive bias temperature instability (PBTI) effect. Particularly for short transistors stressed at high temperatures, this PBTI component dominates the total CHC degradation.

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

The effects of negative bias temperature instability (NBTI) on the performance of a CMOS inverter have been investigated by means of both simulation and experimental methods. The simulation of NBTI effects on CMOS inverter has been done by shifting the pFET V tho BSIM parameter. The results show that NBTI shifts the inverter transfer curve, reduces the low noise margin and current consumption but increases the high noise margin. A good agreement between simulation and experimental results has been obtained. Therefore, it can be assumed that the effect of NBTI on CMOS circuits can be mainly predicted by shifting the V tho pFET parameter.

Positive Bias Temperature Instability Effects in nMOSFETs With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

The positive bias temperature instability (PBTI) and the stress-induced leakage current (SILC) effects are thoroughly examined in nFETs with SiO2/HfO2/TiN dual-layer gate stacks under a wide range of bias and temperature stress conditions. Experimental evidence of the SILC increase with time is obtained suggesting the activation of a trap generation mechanism. Threshold voltage (V T) instability is found to be the result of a complicated interplay of two separate mechanisms; filling of preexisting electron traps versus trap generation each one dominating at different stress condition regimes. Furthermore, V T instability relaxation experiments, undertaken at judiciously chosen conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have similar characteristics. Finally, it is shown that the role of the SILC effect (and the associated trap generation component) on V T instability is process dependent and that SILC reduction is accompanied by enhancement of the PBTI device lifetime.

Performance, Reliability, Radiation Effects, and Aging Issues in Microelectronics - From Atomic-Scale Physics to Engineering-Level Modeling

The development of engineering-level models requires adoption of physical mechanisms that underlie observed phenomena. This paper reviews several cases where parameter-free, atomic-scale, quantum mechanical calculations led to the identification of specific physical mechanisms for phenomena relating to performance, reliability, radiation effects, and aging issues in microelectronics. More specifically, we review recent calculations of electron mobilities that are based on atomic-scale models of the Si-SiO2 interface and elucidate the origin of strain-induced mobility enhancement. We then review extensive work that highlights the role of hydrogen as the primary agent of reliability phenomena such as Negative Bias Temperature Instability (NBTI) and radiation effects, such as Enhanced Low Dose Radiation Sensitivity (ELDRS) and dopant deactivation. Finally, we review atomic-scale simulations of recoils induced by energetic ions in Si and SiO2. The latter provide a natural explanation for single-event gate rupture (SEGR) in terms of defects with energy levels in the SiO2 band gap.

Strain effect and channel length dependence of bias temperature instability on complementary metal-oxide-semiconductor field effect transistors with high-k/SiO2 gate stacks

The strain effect and channel length dependence of bias temperature instability on dual metal gate complementary metal-oxide-semiconductor field enhanced transistors with HfSiON dielectric were studied in detail. For channel length larger than 0.1 μm, both positive and negative bias temperature instabilities (PBTI and NBTI) were not affected by the tensile strain obviously. As the channel scaling down to less than 0.1 μm, the degradation after PBTI stress was still not influenced by the strain, however, the NBTI degradation was enhanced significantly. In addition, the dependence of BTI on channel length was extensively investigated under constant voltage and field stress.

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability at both time zero and after NBTI aging increases. The time0 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability. This paper focuses on the bias temperature instability stress-induced device Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability and the trend across several technology generations. The remarkable correlation of aging-induced Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.