Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs

Abstract

The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p-channel metal–oxide–semiconductor field-effect transistor using high-k/metal gate stacks is investigated. The direct current–current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage.