Two concerns about NBTI issue: gate dielectric scaling and increasing gate current

Abstract

In order to obtain a clear perspective concerning the negative bias temperature instability (NBTI) issue toward 65-nm-node and beyond, (1) the impact of thinning gate dielectric on the basic mechanism of NBTI and (2) the influence of gate electron current on NBTI degradation rate have been investigated. Both were studied with focus on the hydrogen release reaction. This is believed to be the origin of NBTI. By studying the diffusion behavior of released hydrogen, we have clarified that our experimental results of NBTI degradation obtained under voltage-accelerated conditions can be explained by the widely accepted diffusion-controlled model without taking the influence of the gate electrode interface into account even in the case of sub-nm SiON gate dielectrics. However, from numerical calculations, it has been shown that the effect of the gate electrode interface on the diffusion behavior of released hydrogen should be taken care of at stress voltage as low as that of practical operation. In particular, the possibility of NBTI worsening due to thinning gate dielectric has been suggested especially for low stress voltage. To foresee this NBTI worsening and to evaluate NBTI lifetime precisely, we have proposed temperature-acceleration test instead of voltage-acceleration test. Next, by studying NBTI of n+gate-pMOSFET in which the influence of gate electron current is dramatically emphasized, it has been examined whether electron current flowing through gate dielectric will affect NBTI or not. Although the primary driving force of NBTI is considered to be the electric field, electron tunneling current that flows under NBT stress has been shown to worsen NBTI via the suppression of the reverse reaction of hydrogen release.