Berkeley Short-channel IGFET Model Research Articles

Threshold Inverter Quantizer-Based 2-Bit Comparator using Spatial Wavefunction Switched (SWS) FET Inverters: Power Dissipation Analysis

This paper aims to assess the power dissipation of a threshold quantizer (TIQ) 2-bit-based comparator using a SWS-FET-based inverter [1, 2, 4, 5]. Unlike conventional comparators, SWS-based comparator functionalized with TIQ comprises two or more vertically stacked quantum dots or well channels [1-3, 5, 6]. Herein, power dissipation analysis of the simulated circuit is carried out using Cadence by integrating the Berkeley Short-Channel IGFET Model (BSIM) and the analog behavioral model (ABM) [1,3,4,9]. The transient behavior of the inverter circuit is evaluated using 180 nm technology node. Our results demonstrated a significant reduction in power dissipation which overcome the limitation of previous 4-state logic implementations.

Well-Balanced Ambipolar Charge Transport of Diketopyrrolepyrrole-Based Copolymers: Organic Field-Effect Transistors and High-Voltage Logic Applications.

A poly (3,6-bis(thiophen-2-yl)-2,5-bis(2-decyltetradecyl)-2,5-dihydropyrrolo[3,4-c]pyrrole-1,4-dione-co-(2,3-bis(phenyl)acrylonitrile)) (PDPADPP) copolymer, composed of diketopyrrolopyrrole (DPP) and a cyano (nitrile) group with a vinylene spacer linking two benzene rings, is synthesized via a palladium-catalyzed Suzuki coupling reaction. The electrical performance of PDPADPP in organic field-effect transistors (OFETs) and circuits is investigated. The OFETs based on PDPADPP exhibit typical ambipolar transport characteristics, with the as-cast OFETs demonstrating low field-effect hole and electron mobility values of 0.016 and 0.004cm2 V-1 s-1 , respectively. However, after thermal annealing at 240°C, the OFETs exhibit improved transport characteristics with highly balanced ambipolar transport, showing average hole and electron mobility values of 0.065 and 0.116cm2 V-1 s-1 , respectively. To verify the application of the PDPADPP OFETs in high-voltage logic circuits, compact modeling using the industry-standard small-signal Berkeley short-channel IGFET model (BSIM) is performed, and the logic application characteristics are evaluated. The circuit simulation results demonstrate excellent logic application performance of the PDPADPP-based ambipolar transistor and illustrate that the device annealed at 240°C exhibits ideal circuit characteristics.

Propagation Delay and Power Dissipation Analysis for a 2-Bit SRAM Using Multi-State SWS Inverter

This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.

Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

Analytical Parasitic Resistance and Capacitance Models for Nanosheet Field-Effect Transistors

We developed analytical compact models of parasitic resistance and capacitance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> ) for nanosheet field-effect transistors (NSFETs) with metal contact structures. The proposed model accurately captures the number of sheets, sheet geometry, gate, source, drain, and contact sizes. The parasitic resistance model generated in each region was modeled using the transmission line method (TLM) and the spread resistance model. The parasitic capacitance model was modeled using the conformal mapping method based on the distribution of the electric field. The developed models were validated by changing the structural parameters. The proposed models were implemented in Berkeley short-channel IGFET model (BSIM)-common multi-gate (CMG) to enable circuit performance prediction. With our proposed model, we can accurately predict the circuit performance of NSFETs, capturing the recent scaling trends and process variations in the proposed NSFET.

Neural Network-Based BSIM Transistor Model Framework: Currents, Charges, Variability, and Circuit Simulation

We present a neural network (NN)-based transistor modeling framework, which includes drain, source, and gate currents and charges and their variabilities. The training data are generated by a Berkeley short-channel IGFET model (BSIM) with ranges of channel lengths, widths, and oxide thicknesses. The NNs are trained to learn the geometry dependence. The drain, source, and gate currents are modeled with one NN and the charges by another NN. The NNs are trained to produce accurate variability prediction and derivatives of currents and charges. Quality and robustness tests, such as Gummel symmetry, harmonic balance, and ring oscillator, are performed and show excellent results.

Behavioral modeling for low-voltage pentacene-based OTFTs and their implementations for organic logic circuits

We present a behavioral compact model and its implementation for low-voltage pentacene-based organic thin film transistors (OTFTs) using industry standard BSIM4 (Berkeley Short-channel IGFET Model) in LTspice platform. First, we simplify the number of BSIM4 model parameters according to the device structure. On the other hand, we adapt the BSIM4 mobility equation to OTFT and also involve the off-current using two behavioral current sources. Then, we perform metaheuristics-based optimization to extract the related BSIM4 model parameters together with additional four parameters, introduced in this work, fitting the modified model to the experimental data of an OTFT, using pentacene active layer. Finally, we implement the behavioral compact model in LTspice and validate its usage for low-voltage pentacene-based OTFTs comparing the experimental and modeled current–voltage curves. In this study, we also successfully simulate OTFT implementations of a Pseudo-E inverter, a Pseudo-E NAND gate, and a 1-bit full adder circuit based on NAND gates using our behavioral OTFT model and then investigate the static and dynamic performance parameters of these circuits. The supply voltage is 3 V and maximum frequency of the inputs is 500 Hz in the simulations.

Robust Compact Model of High-Voltage MOSFET’s Drift Region

This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.

A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components

FDSOI (Fully Depleted Silicon On Insulator) devices have a good performance in anti-single-event circuits. However, the bipolar amplification effect becomes a severe problem due to the buried oxide. The previous models for Single Event Transient (SET) of FDSOI did not fully consider the current of all components. Most importantly, they did not take the influence of the back-gate voltage into account. Thus, this paper presents a modeling method for the SET current in FDSOI MOSFET where all three components are modeled individually. The prompt current and diffusion current are modeled with a current source respectively. The Berkeley Short-channel IGFET Model for Silicon-on-Insulator (BSIMSOI) model is integrated into this model to calculate the bipolar amplification current. Compared to using the bipolar transistor model, this method avoids additional current input from the base electrode. It is more consistent with the mechanism of bipolar amplification effect for FDSOI devices without body contact. Instantaneously, an improved model is proposed that considers the influence of the back-gate voltage on the SET of the FDSOI devices. All models are validated through Technology Computer Aided Design (TCAD)simulation results.

Ferroelectric Field-Effect Transistors for Binary Neural Network With 3-D NAND Architecture

Ferroelectric field-effect transistor (FeFET) can be operated as a nonvolatile memory device with low programming voltage based on polarization. In particular, it can be used as a synaptic device in a neuromorphic system based on the NAND flash array structure. We demonstrate a Hf0.5Zr0.5O2 (HZO)-based FeFET device fabricated on a silicon-on-insulator (SOI) substrate with high ON/OFF ratio and reliability characteristics. The HZO-based FeFET is utilized as a synaptic device based on the 3-D NAND architecture. It is verified with the binarization of input–output signals and weight value for efficient vector–matrix multiplication (VMM) operation using the 3-D NAND architecture. In addition, a neural network layer-mapping method increasing synaptic cell efficiency is proposed. A system-level simulation is performed based on the FeFET single-device experimental data. The VMM operation is verified through the SPICE Berkeley short-channel IGFET model (BSIM), and off-chip (ex-situ) learning with binary neural network (BNN) is performed for the Modified National Institute of Standards and Technology Database MNIST and fashion-MNIST data. The results confirm that the proposed FeFET-based BNN can perform accurate VMM operations and is robust to variations due to the binary weight state.

A Subcircuit-Based Model for the Accumulation-Mode MOS Capacitor

The accumulation-mode metal-oxide-semiconductor (MOS) capacitor is commonly employed to implement MOS varactors in frequency-tuning circuits for radio frequency (RF) and analog applications. A subcircuit model for the accumulation-mode MOS (AMOS) capacitor based on the Berkeley Short-channel IGFET Model (BSIM) for the MOS field effect transistor (MOSFET) is presented. The proposed model accurately fits the capacitance-voltage (C-V) characteristics of an AMOS capacitor fabricated in a submicron CMOS process over the full range of operating gate voltages. The model also accounts for the impact of the distributed series resistance on the transient response of the AMOS capacitor. Notably, the gate capacitance and the associated series resistance are modeled as a distributed resistor-capacitor (RC) network to derive a subcircuit-based model with the bias-dependent resistance of the accumulation layer modeled as a voltage-controlled resistor (VCR). The proposed model is evaluated based on SPICE simulation of the intrinsic transient response of the AMOS capacitor using a basic circuit, representing the distributed RC network associated with the MOS device structure. Fine tuning of the effective series resistance in the subcircuit model can be achieved by fitting the measured data characterizing the charge–discharge behavior of the AMOS capacitor to the simulated data characterizing the intrinsic transient response generated by SPICE.

A Compact Model of Ferroelectric Field-Effect Transistor

In this letter, we present a compact model of ferroelectric field-effect-transistor (FEFET). The model consists of a ferroelectric (FE) capacitor model and a Berkeley Short-channel IGFET Model (BSIM), a standard SPICE MOSFET model. The FE model, similar to the nucleation-limited-switching model, is based on the statistical multidomain dynamics of FE materials. The charge equality between FE and MOSFET is satisfied through the SPICE simulator. The model reproduces the steep switching in the reverse bias region observed in experimental FEFETs and the current drop at both major loop and minor loop switching. A versatile inverted-memory-window (IMW) model can model the IMW behavior of FEFET that may be caused by charge trapping. We demonstrate that the reported model can accurately fit the published data of Fin-FEFET and FDSOI-FEFET under different bias conditions.

Prediction Methodology for Next-generation Device Characteristics using Machine Learning

In this article, we propose a prediction methodology for next-generation device characteristics for process design kit (PDK) models that utilize various machine learning algorithms to achieve high accuracy and reduction of development turn-around time (TAT). The Berkeley short-channel IGFET model (BSIM) is used for generating datasets, while n-channel MOSFET compact model is used for peripheral circuits in dynamic random-access memory (DRAM) technology. Datasets for training comprise device characteristics that use compact models in present-generation products. In addition, a compact model of next-generation products is used for validating datasets. We demonstrate that our prediction methodology using random forest regression provides high accuracy of less than 0.7% RMSE and reduces development TAT.

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor in a 14 nm FinFET CMOS Process.

In this work, a compact model is presented for a 14-nm CMOS-based fin resonant body transistor (fRBT) operating at a frequency of 11.8 GHz and targeting radio frequency (RF) generation/filtering for next-generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of displacement component coupling due to the periodic nature of the back-end-of-line (BEOL) metal phononic crystal (PnC). An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the Berkeley short channel IGFET model (BSIM)-common multigate (CMG) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible toward change in transduction mechanisms and device architecture. Ultimately, the behavior is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.

Power Dissipation and Cell Area: Quaternary Logic CMOS Inverter vs. Four-State SWS-FET Inverter

Power dissipation of spatial wave function switched (SWS) FETs four-state inverter is the focus of this paper. The current can flow through multiple channels in a (SWS)-FETs, which comprises vertically stacked quantum well/quantum dot channels. Using four voltage levels, the four-state SWS transistor inverter circuit is simulated. Cadence was used to perform SWS-FET inverter circuit simulations to evaluate power dissipation. To develop the SWS-FET model, an Analog Behavioral Model (ABM) and the Berkeley Short-Channel IGFET Model (BSIM4.6) were combined. To evaluate the inverter circuit’s transient behavior, a 0.18-μm technology node was used. The improvement in power dissipation, the frequency of operation, and reduction in cell area are all approximately is by a factor of 2-3. As a result, circuits based on SWS-FET inverters overcome the limitations of earlier implementations of 4-state logic circuits.

Propagation Delay Evaluation for Spatial Wavefunction Switched (SWS) FET-Based Inverter

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures

We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers.

Bulk-Referenced Metal-Oxide Semiconductor Transistor Modeling With BSIM: A Systematic Approach to Facilitate Symmetric Characteristics

In High-Performance Radio-frequency (RF) circuits design, accurate modeling of harmonic distortion characteristics is very important. For this purpose, the bulk-referenced Berkeley Short-Channel IGFET Model (BSIM)-Bulk model is better than the source-referenced BSIM4 model in using planar metalnoxide semiconductor (MOS) technology nodes, such as the 45/40-nm node, the 32/28-nm node, and the 22/20-nm node by integrated circuit (IC) foundries, e.g., TSMC and Samsung. It can fulfill all symmetry tests. The first-order, second-order, and third-order partial derivatives of drain current with respect to drain-source voltage are continuous at V DS equal to zero.

Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n- and p-channel spatial wavefunction-switched field-effect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS–ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of high-mobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output–input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented.