Basis Of FPGA Research Articles

IMPLEMENTATION OF A MATCHED FILTER FOR LFM SIGNALS USING A SYSTEM-ON-CHIP BASED SDR TRANSCEIVER

Background. Creation of communication channels with effective protection against intentional interference is the most urgent task for communication channels of unmanned aerial vehicles (UAVs). An effective solution is the use of signals with spectrum expansion, which allows reducing the impact of intentional interference on control and telemetry channels, thereby increasing the survivability of UAVs. The most optimal is the use of LCM modulation, which became possible with the development of SDR and SoC technologies. The main problem of using LFM modulation is the complexity of implementing matched filters. This requires research to create optimal digital implementations of matched filters. Objective. The purpose of the paper is to determine the parameters of the LFM signal for the implementation of the communication system using CSS modulation on the SDR transceiver. Optimal implementation of discrete matched filter (correlator) for CSS BOK modulation on FPGA (SoC). Methods. Analysis of the possibilities of implementing CSS BOK modulation for building a communication system based on SDR transceivers. Analysis of optimal options for building a discrete matched filter (correlator) for CSS BOK modulation on FPGA (SoC) and its implementation. Testing on a laboratory bench. Results The possibility of creating a communication system based on an SDR transceiver using CSS BOK modulation has been confirmed. The optimal parameters of the LFM signal, which can be implemented, have been studied. An implementation of a discrete matched filter (correlator) for CSS BOK modulation on FPGA has been developed. Testing carried out on a laboratory bench using SDR transceivers AD9361 (AD9364) showed the correctness and effectiveness of the decisions made. Conclusions The parameters of the LFM signal for the implementation in the communication system using CSS modulation on the SDR transceiver have been studied and determined. It was determined that when using the AD9361 (AD9364) transceiver, it is possible to implement an LFM signal with a band of up to 25 MHz, while the optimal symbol duration will be 16.6667 µsec at 1024 counts and a sampling frequency of 61.44 MHz. It was determined that the best CSS modulation method for creating a communication system is the binary orthogonal manipulation (BOK) method, which allows you to effectively use the advantages of SDR technologies, in particular, the ease of working with quadrature channels and, as a consequence, the ease of implementing phase synchronization. It has been determined that the best method of implementing a matched filter (correlator) on the basis of FPGA (SoC) is the application of fast convolution based on the fast Fourier transform. The developed implementation of a discrete matched filter (correlator) for CSS BOK modulation on FPGA showed the possibility of implementing a communication system with CSS BOK modulation on an SDR transceiver in full accordance with the research results. Experimental studies were carried out on a laboratory bench using SDR transceivers AD9361 (AD9364), which fully confirmed the results of simulation modelling.

SYNTHESIS OF VHDL-MODEL OF A FINITE STATE MACHINE WITH DATAPATH OF TRANSITIONS

Context. The problem of building a program model of a finite state machine with datapath of transitions using VHDL language is considered. The model synthesis process is identified with the synthesis of this type of finite state machine, since the built model can be used both for the analysis of the device’s behavior and for the synthesis of its logic circuit in the FPGA basis. The object of the research is the automated synthesis of the logic circuit of the finite state machine with the datapath of transitions, based on the results of which numerical characteristics of the hardware expenses for the implementation of the state machine circuit can be obtained. This makes it possible to evaluate the effectiveness of using this structure of the finite state machine when implementing a given control algorithm.
 Objective. Development and research of a VHDL model of a finite state machine with datapath of transitions for the analysis of the behavior of the state machine and the quantitative assessment of hardware expenses in its logic circuit.
 Method. The research is based on the structural diagram of a finite state machine with datapath of transitions. The synthesis of individual blocks of the structure of the state machine is carried out according to a certain procedure by the given graph-scheme of the con-trol algorithm. It is proposed to present the result of the synthesis in the form of a VHDL description based on the fixed values of the states codes of the state machine. The process of synthesizing the datapath of transitions, the block of formation of codes of transitions operations and the block of formation of microoperations is demonstrated. VHDL description of that blocks is carried out in a synthesizable style, which allows synthesis of the logic circuit of the finite state machine based on FPGA with the help of modern CAD and obtaining numerical characteristics of the circuit, in particular, the value of hardware expenses. To analyze the correctness of the synthesized circuit, the process of developing the behavioral component of the VHDL model, the function of which is the generation of input signals of the finite state machine, is considered. The classical combination of the synthesizable and behavioral parts of the model allows presenting the results of the synthesis of a finite state machine with datapath of transitions as a separate project that can be used as a structural component of the designed digital system.
 Results. Using the example of an abstract graph-scheme of the control algorithm, a VHDL model of a finite state machine with datapath of transitions was developed. With the help of CAD AMD Vivado, a synthesis of the developed model was carried out and behavioral modeling of the operation of the finite state machine circuit was carried out. The results of the circuit synthesis made it possible to obtain the value of hardware expenses when implementing the circuit in the FPGA basis. According to the results of behavioral modeling, time diagrams were obtained, which testify to the correctness of the implementation of the functions of transitions and outputs of the synthesized state machine.
 Conclusions. In traditional VHDL models of finite state machines, the states do not contain specific codes and are identified using literals. This allows CAD to encode states at its own discretion. However, this approach is not suitable for describing a finite state machine with datapath of transitions. The transformation of states codes using a set of arithmetic and logic operations requires the use of fixed values of states codes, which determines the specifics of the VHDL model proposed in this paper. This and similar models can be used, in particular, in the study of the effectiveness of a finite state machine according to the criterion of hardware expenses in the device circuit.

Separation of Input Variables for Optimization of the Mealy FSM Circuit

Introduction. One of the most important blocks of almost any digital system is the control device (CU), since the characteristics of the CU largely determine the characteristics of the system as a whole. In the practice of engineering design, the behavior of the CU is often specified using the Mealy finite state machine (FSM) model. A feature of Mealy FSM is the dependence of systems of Boolean functions that define the circuit on FSM inputs and states. In this article, this feature is taken into account when optimizing the characteristics of FSM circuit in the basis of FPGA chips. When developing FSM circuits, it is necessary to optimize its characteristics, such as performance and hardware costs. FPGAs are one of the most common logic bases for implementing digital systems. FPGA components such as look-up table (LUT) elements, programmable flip-flops, embedded memory blocks (EMBs), and programmable interconnects are sufficient to implement the CU circuit. The purpose of the article. In this paper, we propose a method for reducing hardware costs in the Mealy FSM cirucit implemented in the FPGA basis. In this case, the problem of implementing a circuit in a mixed elemental basis is considered. A mixed basis is understood as the joint use of LUTs and EMBs. The situation is considered when the number of available EMBs is extremely limited, which is quite possible, since EMBs are widely used to implement various operating blocks of digital systems. The main disadvantage of LUTs is the small number of inputs. Modern digital systems can generate signals of logical conditions entering the CU, the number of which is tens of times greater than the number of LUT inputs. This discrepancy between the characteristics of the control algorithm and the number of inputs of the LUTs leads to multilevel CU circuits with an irregular structure of programmable interconnections. To optimize multilevel schemes, the method of replacing input variables is used with the joint use of LUTs and EMB blocks. Results. The analysis of the effectiveness of the proposed method was carried out using the libraries of standard benchmarks FSMs and the Vivado CAD platform. Studies have shown that the proposed method makes it possible to reduce the number of LUTs in the range from 100% to 82%. For 37% of automata, the method of replacing input variables can be applied only in conjunction with the separation of input variables. Conclusions. The proposed method makes it possible to reduce hardware costs (the number of LUTs and their interconnections), delay time, and power consumption. The article shows the conditions for applying the proposed method. The results of studies of the effectiveness of the proposed method for standard automata using chips of the Virtex-7 family and the Vivado industrial package are presented. Keywords: finite state machine, synthesis, FPGA, EMB, LUT, input replacement.

Research of the possibility of increasing the uniqueness of determining the time delay of the phase-code shift keyed signal in a correlation meter on the basis of FPGA

Background. In radar systems, phase code-domain keying signals are widely used. Continuous signals of this kind have the advantage of low side lobes of the cross-correlation function and high noise immunity, but have limitations on the size of the area of view associated with the presence of ambiguity peaks. Aim. The paper considers the possibility of increasing the unambiguity of determining the time delay of the phase-code shift keyed signal in a correlation meter based on a combined FPGA-based coding rule. Methods. To achieve this goal, a numerical simulation of a correlation time delay meter with modulating signals formed by different coding rules was performed. Results. It is proposed in the correlation meter with continuous reception of the phase-code shift keyed signal to improve the accuracy of measuring the time delay and the unambiguity of determining the location of remote objects, as a modulating signal, use a signal formed by two pseudo-random sequences that are the same according to the coding rule, but different in duration. The results of numerical simulation of the post-detection digital processing system based on the proposed method are presented. Conclusion. The application of the proposed coding rule makes it possible to implement a correlation meter with a minimum amount of computing resources while increasing the unambiguity and expanding the range of measured time delays.

Development of a simulation model in the power conversion channel out of the solar-hydrogen power supply system installed in the spacecraft with implementation on the basis of FPGA

The article describes the method of synthesis of the simulation model of pulse converters with the control system, intended for implementation in FPGA. The technique is based on the structural representation of integro-differential and algebraic equations and the method of switching breaking functions. The models you develop allow you to bring modeling time closer to real. The method is described by an example of a solar battery energy conversion channel of an automatic spacecraft power supply system. The paper considers the possibility of implementing a solar-hydrogen energy supply scheme. This concept involves the accumulation of excess energy in the form of chemical energy on board the spacecraft.

Approach to positional logic algebra

The method of Boolean function representation in terms of positional logic algebra in compact operator form is offered. Compared with the known method, it uses position operators with a complexity of no more than two and only one type of equivalent transformations. The method is less labor intensive. It allows parallelizing logic calculations. The corresponding way of Boolean function implementation is developed. It competes with some known ways in terms of hardware complexity, resource intensity, and speed when implemented on an FPGA basis. Possibilities open up for creating effective automating means of representing Boolean functions from a large number of variables, synthesizing the corresponding LCs, and improving modern element bases.

SYNTHESIS OF THE FINITE STATE MACHINE WITH DATAPATH OF TRANSITIONS ACCORDING TO THE OPERATIONAL TABLE OF TRANSITIONS

Context. The problem of formalizing the description of a microprogram finite state machine based on the principle of operational transformation of state codes with the help of a modified transition table is considered. The object of research was a model of a microprogram finite state machine with datapath of transitions.
 Objective. The goal of the work is development and research of a method for formally specifying a microprogram finite state machine with datapath of transitions in the form of a modified table of transitions containing sufficient information for synthesizing the logic circuit of the finite state machine in the basis of programmable logic devices.
 Method. A new way of representing the formal solution of the problem of algebraic synthesis of a microprogram finite state machine with datapath of transitions in the form of an operational table of transitions is proposed. This table is a modification of the direct structural table traditionally used in the synthesis of microprogram finite state machines. The use of the previously known representation of the formal solution of the problem of algebraic synthesis in the form of a system of isomorphisms of automaton algebras is too formalized and makes it difficult to synthesize the logical circuit of the finite state machine due to the separate description of the transition and output functions. It is shown that the structure of a microprogram finite state machine with datapath of transitions requires information about the set of interpretations of state codes and the transition operations used to be entered into the traditional table of transitions. It is noted that the proposed operational table of transitions contains sufficient information for the synthesis of the logical circuit of the finite state machine. An example of constructing an operational table of transitions for a finite state machine given by a graph-scheme of the implemented control algorithm is shown. The example demonstrates various ways to interpret state codes. The procedure for synthesizing the circuit for generating codes of transition operations and the circuit for generating microoperations according to the operational table of transitions is proposed.
 Results. An example of the implementation of the main stages of the synthesis of a finite state machine with datapath of transitions according to the operational table of transitions is considered. Examples of synthesized finite state machine models in the VHDL language are given, which take into account the peculiarities of the representation of finite state machine models in Xilinx Vivado CAD. The results of the synthesis of the finite state machine according to VHDL models in FPGA basis are shown.
 Conclusions. The experiments carried out confirmed the sufficiency of the operational table of transitions for describing a microprogram finite state machine with operational transformation of state codes for the purpose of further synthesizing its logic circuit. Prospects for further research are the use of the proposed operational table of transitions in the development of various methods for the synthesis and optimization of microprogram finite state machine with operational transformation of state codes.

НЕЙРОКОМПЬЮТЕРНОЕ УПРАВЛЕНИЕ ПРОПУСКНОЙ СПОСОБНОСТЬЮ КАБЕЛЬНЫХ СЕТЕЙ ПОСРЕДСТВОМ УЧЕТА И КОНТРОЛЯ ИХ ПАРАМЕТРОВ

The article discusses a neurocomputer system for predicting the resource of a power cableline (РCL) using neural network technologies. A hardware modular implementation of aneurocomputer (NC) implemented on the basis of FPGA was selected. To solve the problem ofpredicting thermal processes of РCL, it was decided to use a NeuroMatrix NM6404 digitalneurochip with a variable structure due to their high performance compared to power consumption,a high degree of versatility. To predict the temperature conditions of the РCL, an artificialneural network (INS) was developed to determine the current temperature regime for the currentcarryingcore of the РCL. The architecture of the INS for the implementation of the NC of the SCLtemperature prediction system has been selected, which allows for long-term prediction of РCLtemperatures in real time. The choice of the activation function of the INS neurons for the implementationof the NC of the SCL temperature prediction system, which allows for a long-term forecastof SCL temperatures without increasing the error with an increase in the forecast range. Theproposed neural network algorithm that predicts the characteristics of the electrical insulation ofthe РCL, based on the sliding window method for predicting time series, was tested on a controlsample of experimental data not included in the sample for training the INS. Experimental studiesof the proposed adaptive forecasting method have been carried out, namely, an adaptive algorithmhas been developed and the prediction of thermal processes in the isolation of the SCL from theload current has been performed. Analysis of the results showed that the longer the aging time, thegreater the temperature difference between the original and aged sample. When analyzing thedata obtained, it was determined that the maximum deviation of the data obtained from the INSduring the experiment from the data in the training sample was less than 3%, which is quite acceptablefor this study result. It is shown that the developed methods and algorithms are elementsof an integrated power grid management system, and the developed adaptive NC model makes itpossible to assess the current state of insulation and predict the remaining life of the РCL.

РЕАЛИЗАЦИЯ В БАЗИСЕ ПЛИС РЕЛЯТОРНЫХ КОНТРОЛИРУЮЩИХ ОПРОСНЫХ УСТРОЙСТВ ЦИФРОВЫХ СИГНАЛОВ

The requirements for modern means of technical control and functional diagnostics ofequipment for critical applications are formulated, one of which is the processing of diagnosticinformation at a real-time pace. It is noted that for working with digital diagnostic signals, relational monitoring polling devices based on the apparatus of ordinal logic, which gives a significanttime gain over traditional binary logic, are promising. The hardware implementation of ordinal-logical polling devices in the FPGA basis, along with the obvious advantages of the developmentstage, will allow for operational reconfiguration of the internal structure to adapt to thechanging operating conditions of the control object. The hardware implementation of two knowndevices is considered. A variable priority device is used to identify the sensor that has detected afailure or malfunction, with the possibility of setting the sensor number from which the survey willbegin, and the direction of traversing the sensor tuple. The device of centralized control of a groupof objects is used to search for an extreme (maximum or minimum) digital diagnostic signal withsimultaneous determination of the number of the corresponding sensor in one clock cycle of themonitoring and diagnostic system. The development of combinational data schemes of monitoringsurvey devices was carried out by means of ISE Design Suite 14.7. The positive results of testingthe algorithms of the created models are presented, summarized in tables of the states of the inputsand outputs of the circuits and illustrated by time diagrams of binary signals at the terminals ofthe circuits. An estimate of the required FPGA resource costs is given, expressed in the number oflogical elements and user contacts. Also, using the example of low integration devices and themost resource-intensive samples, the upper and lower estimates of the number of FPGAs of varioustypes of the Xilinx Spartan-6, Xilinx Virtex-4 families and the domestic 5576/5578 series ofJSC KTC Electronics are given. It is established that with the number of diagnostic sensors up to200, depending on the FPGA family, up to 17 low integration chips and up to 7 resource-intensivechips are required to implement one monitoring polling device.

Methods for Change Parallelism in Process of High-level VLSI Synthesis

In this paper methods for increasing the efficiency of VLSI development based on the method of architecture-independent design are proposed. The route of high-level VLSI synthesis is considered. The principle of constructing a VLSI hardware model based on the functional-flow programming paradigm is stated.The results of the development of methods and algorithms for transformation functional-parallel programs into programs in HDL languages that support the design process of digital chips are presented. The principles of assessment are considered and the classes of resources required for the analysis of design solutions are identified. Reduction coefficients and methods of their calculation for each resource class have been introduced. An algorithm for calculating the reduction coefficients and estimating the required resources is proposed. An algorithm for converting parallelism is proposed, taking into account the specified constraints of the target platform. A mechanism for the exchange of metrics with an architecture-dependent level has been developed. Examples of parallelism reduction for the FPGA platform and practical implementation of FFT algorithms in the Virtex® UltraScale FPGA basis are given. The developed methods and algorithms make it possible to use the method of architecture-independent synthesis for transferring VLSI projects to various architectures by changing the parallelism of the circuit and equivalent transformations of parallel programs. The proposed approach provides many options for hardware solutions for implementation on various target platforms.

RADIO COMMUNICATION CHANNEL WITH FREQUENCY MODULATED SIGNAL BASED ON PROGRAMMABLE LOGICAL INTEGRATED CIRCUIT

This paper presents the results of an experimental study of a radio communication channel (RF) with a frequency-modulated signal based on a programmable logic integrated circuit (FPGA). The work highlights the features of hardware and software implementation of algorithms for the synthesis of frequency-modulated signal and demodulation of this signal using FPGA in real time. The software part is made in the development environment of ISE WebPack 14.7 in Verilog language with the ability to visualize the results of GTKWave. Hardware implementation is performed on the basis of FPGA (Spartan-6) using a debug board from Alinx AX309.
 The experimental study consists of two stages of the study of the FM oscillator modulator and the synchronous FM oscillator demodulator. In the course of research, the amplitude spectral characteristics of the signals (amplitude spectra) were obtained: at the output of the modulator and demodulator of the frequency-modulated signal, which have good agreement with the simulation results. The quality of the hardware synchronous demodulation of the FM signal based on the phase tuning system was confirmed by the result of the obtained spectrum of the restored information signal, in which the ratio between the first harmonic and the second is 51.87 dBm. When obtaining the results of experimental studies of the RH system, it was found necessary to take into account the peculiarities of the arithmetic of integers, which make errors in the hardware implementation of DSP algorithms.
 Thus, the use of programmable logic integrated circuits at the present stage of development of telecommunications and radio engineering opens wide opportunities for the construction of high-speed digital RH systems with parallel signal processing in real time.

Method of reducing the number of LUT elements in the scheme of a composition microprogram control unit with address transformers

In advance digital systems, implemented using various VLSI circuits, an important issue remains to reduce the area of the circuit, which is occupied by the control device, and, consequently, reduce the delay time and the amount of power consumption. As a rule, reducing the area of the circuit of the control device allows improving its other characteristics. Methods for solving this problem to some extent depend on the features of the implemented control algorithm and element basis. The article proposes a method for reducing the number of LUT (Look-Up-Table) elements in the scheme of a composition microprogram control unit (CMCU), based on converting the addresses of the outputs of linear operator circuits (LOC) into output codes. This transformation reduces the number of inputs of the addressing scheme of microinstructions, which is especially important when implementing the circuit of the control device on the FPGA basis due to the small number of inputs of elements of the tabular type LUT. The outputs of the LOC are encoded as elements of some classes of partitioning the set of outputs. This approach allows you to move from a multi-level microinstruction addressing scheme to a two-level one. The control memory and the address conversion block are implemented on embedded memory blocks. The proposed method is an adaptation of the method of double coding of states of Miles automata to the features of CMCU. The method is advisable to use if the microinstruction addressing unit is represented by a multi-level scheme. This is possible if the number of arguments in the memory excitation functions exceeds the number of LUT inputs. If the bit width of the microinstruction address exceeds the number of LUT inputs, then the address converter block circuit is also multilevel. Analysis of standard automata from the library and the Virtex 7 basis showed that this method can be applied to 68% of the library elements. The article considers an example of the synthesis of a CMCU circuit using the proposed method.

Application of a precision programmable DC power supply for spectrometer calibration

The paper presents the circuitry solutions on the basis of which a precision programmable DC power supply was created and tested. The principle of operation of the DC power supply uses a high-precision method of controlling a pulse current stabilizer, based on the adaptation of the duty cycle of the pulse-width modulation (PWM) signal to control the inverter when the load mode changes. From the output of the inverter, the signal is converted by the rectifier into a DC signal with subsequent smoothing of the ripple and enters the load circuit. From a precision low-resistance shunt connected to the load circuit, the signal through the ADC in digital form enters the control unit (CU), implemented on the basis of FPGA, which has a embedded programme for controlling the voltage / current stabilization modes in the load circuit. In addition, the paper shows the use of a precision programmable DC power supply for solving the problem of calibrating the BTC-110S spectrometer. The block diagram of the test stand for spectrometer calibration is presented and relations for the correction of the recorded signals of the thermal radiation spectrum of the objects under study are derived.

Physical principles of operation and basic capabilities of the four channel receiver 1288хк1т (mf-01)

In radar detection and radio navigation ensuring the reception of signals transmitted over the meteor channel of radio communication is often controversial[1-3]. Solving these problems requires the ability to synthesize precision signals directly[4, 5] for heterodyning systems in addition to modern analog-to-digital conversion devices, correlation analysis, and statistical processing of signal-noise complex. The step of adapting four channel receivers to dynamically changing conditions of transmitting information may include determining the composition of the signal-noise mixture, determining the phase characteristics of the communication channel, estimating the channel transmission rate, and obtaining QoS information. In addition, adaptation often implies the use of a logical channel control loop, which entails the need for complex feedback procedures. Software-defined radio systems are radio and telecommunication systems that can be tuned to an arbitrary frequency band and receive various types of modulated signal, consisting of programmable equipment with program control. SDR performs a significant part of digital signal processing on a conventional personal computer, signal processor or FPGA. In such systems and complexes, the parameters are changed by software configuration. The article considers the implementation of DDS for heterodyning an intermediate frequency signal on the FPGA basis for four channel receiver 1288хк1т (mf-01), which allows you to work with both narrow-band and wide-band communication channels (with simultaneous operation of 4 channels, the band can be expanded) and can be used in modern telecommunication communication systems.

Mixed Encoding of Collections of Microoperations for a Microprogram Finite-State Machine

A method is proposed for reducing the number of LUTs in the circuit of a microprogrammed Mealy FSM implemented in a basis of FPGA. The method is based on elimination of some elements from the sets of microoperations for their implementation by EMB. This approach reduces logic levels and interconnections for a circuit implemented with LUTs. An algorithm is proposed for searching for a partition of the set of microoperations. An example of synthesis is given as well as results of the investigations.

РОЗРОБКА ІНТЕРФЕЙСНОГО МОДУЛЯ ДЛЯ ПРОГРАМНО-АПАРАТНОГО КОМПЛЕКСУ АВТОМАТИЧНОЇ КЛАСИФІКАЦІЇ ТЕКСТІВ

The amount of information presented in text form is constantly increasing. A feature of a large amount of such information in most cases is the lack of its structuredness, which complicates the analysis process. At the stage of document processing in the information and analytical system, an automatic classifier is used – as a program, or as a software and hardware complex that accelerates automatic text processing. In this paper, a software and hardware complex is considered, in which the software part functions on the user's computer, and the hardware part is implemented on the FPGA. Thus, the problem of organizing the connection between its two parts is urgent. While FPGAs have high internal parallelism and very high internal bandwidth, the low bandwidth of the interface between the accelerator and the rest of the system, as well as restrictions on the conditions of its use, is a bottleneck in the field of data transfer. This problem is aggravated in the conditions of the need to create a network system for constructing a classifier, where several user computers connected to the network need access to the hardware-implemented part of the complex (accelerator). The aim of this work is to develop an internal interface module with network communication, in accordance with the technical and functional requirements of the software and hardware complex for automatic text classification. Considering the need to provide network access to the accelerator, as a result of the analysis, the Fast Ethernet interface was chosen as the base one. This interface is the most common LAN standard used by most businesses. For the development of the printed circuit board of the interface module, a comprehensive computer-aided design system Altium Designer was used. After the development of the electrical schematic diagram of the project, a simulation of the controller part was created in the Proteus digital-to-analog simulation program. For the convenience of testing the developed interface module, the Arduino UNO module and the SPI serial interface were used. A feature of the developed module is the support of network-level protocols, it makes it possible to organize access from any personal computer of the local network to an expansion board built on the basis of FPGA. The developed printed circuit board of the interface module was analyzed for possible defects and a list of recommendations for the operating conditions of the device was developed. The interface board is designed taking into account the balanced ratio of price-performance criteria, and is intended for use in any institution where there is a need for automatic classification of text documents.

ДОСЛІДЖЕННЯ ОБЧИСЛЮВАЧІВ ПРИСКОРЕНОГО ОБЧИСЛЕННЯ ДАНИХ ЗБІЛЬШЕНОЇ РОЗРЯДНОСТІ НА ОСНОВІ ОДНОВИМІРНОГО КАСКАДУ КОНСТРУКТИВНИХ МОДУЛІВ

Urgency of the research. The study of computers to calculate data of increased bit size and take into account the impact of methods of their description on the implementation of FPGA will increase the speed of data processing, and more efficient use of FPGA resources is certainly an urgent task. Target setting. Accelerating the process of calculating data of increased bit size places additional demands on the implementation of elements of computer systems and computer systems in general. Actual scientific researches and issues analysis. The speed of computing high-bit data used in an FPGA depends on the methods used to describe it, but these methods also affect hardware costs. Uninvestigated parts of general matters defining. There are no theoretical and experimental studies of high-bit computers to calculate the operations of modules based on one-dimensional cascades of structural modules based on FPGA. The research objective. The aim of the work is to describe and study computers of complex operations on the module on the data of the increased bit size in the basis of FPGA. The statement of basic materials. Computers of complex operations on the increased bit module are described by the method of functional description using standard VHDL operators and the method of structural description in the form of a one- dimensional cascade of structural modules. The dependences of speed and hardware costs on the bit are determined experi- mentally taking into account the internal structure of a certain family of FPGAs for each of the methods of description. Conclusions. The use of the method of functional description by typical tools based on FPGA does not allow to take into account the peculiarities of large data processing algorithms, which leads to excessive hardware costs. The proposed method of structural description using a one-dimensional cascade of structural modules in the language of hardware description demonstrates better results and allows a more flexible approach to the use of FPGA hardware resources. Reducing the hardware cost of implementing high-bit computing tools within a particular FPGA, by freeing up additional resources, increases the bit size of the data being processed at no additional cost to replace the hardware with an overall increase in the performance of the computing element or system.

Программно-аппаратные решения повышения сбоеустойчивости комбинационных схем в базисе ПЛИС с учётом межсоединений и блоков ввода-вывода

Программно-аппаратные решения повышения сбоеустойчивости комбинационных схем в базисе ПЛИС с учётом межсоединений и блоков ввода-вывода

Особенности проектирования устройств цифровой обработки сигналов в базисе ПЛИС серии 5578

Особенности проектирования устройств цифровой обработки сигналов в базисе ПЛИС серии 5578

Reduction of hardware costs in the implementation of a Moore FSM circuit on hybrid FPGA

In this paper a method to reduce hardware costs in Moore FSM circuit in the implementation on hybrid FPGA is proposed. The method uses features of Moore FSM and elemental basis of FPGA, and it is based on the use of two sources of classes of pseudoequivalent states due to the large number of inputs of built-in PLA elements in modern hybrid FPGA. Figs.: 3. Refs.: 17 titles.Keywords: reduction of hardware costs; Moore FSM; hybrid FPGA; pseudoequivalent states; PLA elements.