ДОСЛІДЖЕННЯ ОБЧИСЛЮВАЧІВ ПРИСКОРЕНОГО ОБЧИСЛЕННЯ ДАНИХ ЗБІЛЬШЕНОЇ РОЗРЯДНОСТІ НА ОСНОВІ ОДНОВИМІРНОГО КАСКАДУ КОНСТРУКТИВНИХ МОДУЛІВ

Abstract

Urgency of the research. The study of computers to calculate data of increased bit size and take into account the impact of methods of their description on the implementation of FPGA will increase the speed of data processing, and more efficient use of FPGA resources is certainly an urgent task. Target setting. Accelerating the process of calculating data of increased bit size places additional demands on the implementation of elements of computer systems and computer systems in general. Actual scientific researches and issues analysis. The speed of computing high-bit data used in an FPGA depends on the methods used to describe it, but these methods also affect hardware costs. Uninvestigated parts of general matters defining. There are no theoretical and experimental studies of high-bit computers to calculate the operations of modules based on one-dimensional cascades of structural modules based on FPGA. The research objective. The aim of the work is to describe and study computers of complex operations on the module on the data of the increased bit size in the basis of FPGA. The statement of basic materials. Computers of complex operations on the increased bit module are described by the method of functional description using standard VHDL operators and the method of structural description in the form of a one- dimensional cascade of structural modules. The dependences of speed and hardware costs on the bit are determined experi- mentally taking into account the internal structure of a certain family of FPGAs for each of the methods of description. Conclusions. The use of the method of functional description by typical tools based on FPGA does not allow to take into account the peculiarities of large data processing algorithms, which leads to excessive hardware costs. The proposed method of structural description using a one-dimensional cascade of structural modules in the language of hardware description demonstrates better results and allows a more flexible approach to the use of FPGA hardware resources. Reducing the hardware cost of implementing high-bit computing tools within a particular FPGA, by freeing up additional resources, increases the bit size of the data being processed at no additional cost to replace the hardware with an overall increase in the performance of the computing element or system.