Basic Gates Research Articles

Quantum gate control of polar molecules with machine learning.

We propose a scheme for achieving basic quantum gates using ultracold polar molecules in pendular states. The qubits are encoded in the YbF molecules trapped in an electric field with a certain gradient and coupled by the dipole-dipole interaction. The time-dependent control sequences consisting of multiple pulses are considered to interact with the pendular qubits. To achieve high-fidelity quantum gates, we map the control problem for the coupled molecular system into a Markov decision process and deal with it using the techniques of deep reinforcement learning (DRL). By training the agents over multiple episodes, the optimal control pulse sequences for the two-qubit gates of NOT, controlled NOT, and Hadamard are discovered with high fidelities. Moreover, the population dynamics of YbF molecules driven by the discovered gate sequences are analyzed in detail. Furthermore, by combining the optimal gate sequences, we successfully simulate the quantum circuit for entanglement. Our findings could offer new insights into efficiently controlling molecular systems for practical molecule-based quantum computing using DRL.

Biased accumulation based on multiplexer using stochastic correlated logic

AbstractStochastic computing is a non‐traditional computing approach that utilizes stochastic bitstreams to represent numerical values. This representation enables the implementation of circuits using basic logic gates, named stochastic circuits. This work proposes a versatile architecture with correlated input bitstreams for biased accumulation. The design offers a notable reduction in the reliance on random number generators, resulting in lower hardware costs and higher computing accuracy when compared with the existing designs. Experimental results show that the application of Gaussian smoothing has a reduction in area by at least 45% and an improvement in peak signal‐to‐noise ratio of at least 30%.

Interpreting variational quantum models with active paths in parameterized quantum circuits

Variational quantum machine learning (VQML) models based on parameterized quantum circuits (PQC) have been expected to offer a potential quantum advantage for machine learning (ML) applications. However, comparison between VQML models and their classical counterparts is hard due to the lack of interpretability of VQML models. In this study, we introduce a graphical approach to analyze the PQC and the corresponding operation of VQML models to deal with this problem. In particular, we utilize the Stokes representation of quantum states to treat VQML models as network models based on the corresponding representations of basic gates. From this approach, we suggest the notion of active paths in the networks and relate the expressivity of VQML models with it. We investigate the growth of active paths in VQML models and observe that the expressivity of VQML models can be significantly limited for certain cases. Then we construct classical models inspired by our graphical interpretation of VQML models and show that they can emulate or outperform the outputs of VQML models for these cases. Our result provides a new way to interpret the operation of VQML models and facilitates the interconnection between quantum and classical ML areas.

Quantum simulation of dissipation for Maxwell equations in dispersive media

The dissipative character of an electromagnetic medium breaks the unitary evolution structure that is present in lossless, dispersive optical media. In dispersive media, dissipation appears in the Schrödinger representation of classical Maxwell equations as a sparse diagonal operator occupying an r-dimensional subspace. A first order Suzuki-Trotter approximation for the evolution operator enables us to isolate the non-unitary operators (associated with dissipation) from the unitary operators (associated with lossless media). The unitary operators can be implemented through qubit lattice algorithm (QLA) on n qubits, based on the discretization and the dimensionality of the pertinent fields. However, the non-unitary-dissipative part poses a challenge both physically and computationally on how it should be implemented on a quantum computer. In this paper, two probabilistic dilation algorithms are considered for handling the dissipative operators. The first algorithm is based on treating the classical dissipation as a linear amplitude damping-type completely positive trace preserving (CPTP) quantum channel where an unspecified environment interacts with the system of interest and produces the non-unitary evolution. Therefore, the combined system-environment is now closed, and must undergo unitary evolution in the dilated space. The unspecified environment can be modeled by just one ancillary qubit, resulting in an implementation scaling of O(2n−1n2) elementary gates for the total system-environment unitary evolution operator. The second algorithm approximates the non-unitary operators by the Linear Combination of Unitaries (LCU). On exploiting the diagonal structure of the dissipation, we obtain an optimized representation of the non-unitary part, which requires O(2n) elementary gates. Applying the LCU method for a simple dielectric medium with homogeneous dissipation rate, the implementation scaling can be further reduced into O[poly(n)] basic gates. For the particular case of weak dissipation we show that our proposed post-selective dilation algorithms can efficiently delve into the transient evolution dynamics of dissipative systems by calculating the respective implementation circuit depth. A connection of our results with the non-linear-in-normalization-only (NINO) quantum channels is also presented.

Graphene–fullerene heterostructures as robust and flexible nanomechanical bits

Electrical computers have revolutionized society over the past several decades, but questions have remained about their ability to perform in extreme environments, such as their stability at high-temperature conditions. This has motivated the recent surge of interest in developing mechanical computing platforms at all length scales, including the nanoscale, in which traditional electrical computers are augmented with mechanical ones. However, the most proposed nanomechanical bits are volatile memory bits based on the dynamic response of nanomechanical resonators, and as such, there is a need to develop robust and reprogrammable entirely non-volatile nanomechanical bits. Here, we exploit the multiple quasi-stable configurations of the graphene/fullerene/graphene (GFG) van der Waals heterostructure to work as a novel nonvolatile nanomechanical bit. The GFG heterostructure is unique and robust in that it can return to its initial state without further mechanical input, it can be used for logic functions at relevant operating temperatures through simple application of uniaxial strain, it can exhibit reprogrammability between five basic logic gates (NOT, AND, NAND, OR, NOR) by varying the magnitude or direction of applied strain, and it can be used to represent combinatorial logic through full and half adders. These findings provide a new opportunity to develop mechanical computers based on the large class of nanomaterials.

Erasable and Field Programmable DNA Circuits Based on Configurable Logic Blocks.

DNA is commonly employed as a substrate for the building of artificial logic networks due to its excellent biocompatibility and programmability. Till now, DNA logic circuits are rapidly evolving to accomplish advanced operations. Nonetheless, nowadays, most DNA circuits remain to be disposable and lack of field programmability and thereby limits their practicability. Herein, inspired by the Configurable Logic Block (CLB), the CLB-based erasable field-programmable DNA circuit that uses clip strands as its operation-controlling signals is presented. It enables users to realize diverse functions with limited hardware. CLB-based basic logic gates (OR and AND) are first constructed and demonstrated their erasability and field programmability. Furthermore, by adding the appropriate operation-controlling strands, multiple rounds of programming are achieved among five different logic operations on a two-layer circuit. Subsequently, a circuit is successfully built to implement two fundamental binary calculators: half-adder and half-subtractor, proving that the design can imitate silicon-based binary circuits. Finally, a comprehensive CLB-based circuit is built that enables multiple rounds of switch among seven different logic operations including half-adding and half-subtracting. Overall, the CLB-based erasable field-programmable circuit immensely enhances their practicability. It is believed that design can be widely used in DNA logic networks due to its efficiency and convenience.

Novel crosstalk circuit design for high density logic applications

As IC transistors scale down further, physical limitations are restricting performance growth. The contradiction between demands for computing capabilities and challenges in transistor downscaling is exacerbating. This paper proposed a crosstalk circuit design using interconnect coupling capacitance to improve the computing power of chips. Firstly, a valid model of coupling capacitance between metal interconnects is established based on analysis of the factors affecting coupling capacitance. Then, basic crosstalk gates including NAND and NOR are designed by adopting line crosstalk and sampling inverters. Furthermore, complex logic gates and combination circuits are implemented by using the basic crosstalk gates. For verification, a test chip based on line computing is fabricated in 65 nm CMOS technology and the core area is ∼0.019 mm2. The experimental results verified the correctness of the proposed crosstalk gate's logic. Compared with standard logic circuit, the crosstalk NAND or NOR gates reduce the area overhead by 10.6 % and also enhance the circuit's capability of anti-reverse engineering.

Design and engineering of logic genetic-enzymatic gates based on the activity of the human CYP2C9 enzyme in permeabilized Saccharomyces cerevisiae cells

Gene circuits allow cells to carry out complex functions such as the precise regulation of biological metabolic processes. In this study, we combined, in the yeast S. cerevisiae, genetic regulatory elements with the enzymatic reactions of the human CYP2C9 and its redox partner CPR on luciferin substrates and diclofenac. S. cerevisiae cells were permeabilized and used as enzyme bags in order to host these metabolic reactions. We engineered three different (genetic)-enzymatic basic Boolean gates (YES, NOT, and N-IMPLY). In the YES and N-IMPLY gates, human CYP2C9 was expressed under the galactose-inducible GAL1 promoter. The carbon monoxide releasing molecule CORM-401 was used as an input in the NOT and N-IMPLY gates to impair CYP2C9 activity through inhibition of the Fe+2- heme prosthetic group in the active site of the human enzyme. Our study provides a new approach in designing synthetic bio-circuits and optimizing experimental conditions to favor the heterologous expression of human drug metabolic enzymes over their endogenous counterparts. This new approach will help study precise metabolic attributes of human P450s.

The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice

The Gate Level Information Flow Tracking (GLIFT) is an effective method to uphold the information security for high-assurance digital circuits. The GLIFT method associates a security label with each data bit and monitors these labels to expose the illegal information flow in the circuit under tracking. However, the label propagation usually consumes a significant area overhead, especially for the multi-level security lattices. This work aims to reduce the area cost of the GLIFT logic to enhance its applicability. A new implementation technique of GLIFT logic of basic gates is proposed by introducing the logic operation ‘minus’. A decoupling-encoding technique of the security labels is also proposed to simplify the GLIFT logic. Furthermore, three improved GLIFT schemes are introduced for different scenarios based on these two techniques. These improved schemes are applied to some ISCAS’85 benchmarks. The evaluation results show that the improved schemes only consume 38.90%, 39.84% and 29.16% area of that of the original GLIFT scheme on average, respectively.

Development of Autodesk-based Digital Teaching Materials as a Support for Basic Digital Engineering Learning in Vocational Schools

This study aims to design and develop teaching materials for Basic Digital Engineering material in the Basics of Electronics Engineering Subject at the Mechatronics Department of SMKN 4 Malang. Obstacles in learning Basic Digital Engineering, lack of practicum facilities and learning resources, encourage the development of digital teaching materials as a structured solution. Autodesk Tinkercad platform is used to support offline practicum implementation. The purpose of using Autodesk-based learning to encourage students to collaborate and continue to carry out practicum independently outside the school environment. This research includes the development of job sheets consisting of teacher’s handbook and student’s handbook, covering basic logic gates, advanced logic gates, and introduction to microcontrollers. In addition, a guidebook was also developed to optimize the use of Autodesk Tinkercad. This research involves testing the feasibility of job sheets and guidebooks in learning Basic Digital Engineering Materials using the Autodesk Tinkercad platform. The results of this study can contribute to improving the quality of learning and conclude that the use of digital teaching materials with the support of Autodesk Tinkercad can increase student independence in Basic Digital Engineering Materials.

Validation and calibration of a novel GEM biosensor for specific detection of Cd2+, Zn2+, and Pb2+

BackgroundIn this study, we designed a novel genetic circuit sensitive to Cd2+, Zn2+ and Pb2+ by mimicking the CadA/CadR operon system mediated heavy metal homeostasis mechanism of Pseudomonas aeruginosa. The regular DNA motifs on natural operon were reconfigured and coupled with the enhanced Green Fluorescent Protein (eGFP) reporter to develop a novel basic NOT type logic gate CadA/CadR-eGFP to respond metal ions mentioned above. A Genetically Engineered Microbial (GEM)-based biosensor (E.coli-BL21:pJET1.2-CadA/CadR-eGFP) was developed by cloning the chemically synthesised CadA/CadR-eGFP gene circuit into pJET1.2-plasmid and transforming into Escherichia coli (E. coli)-BL21 bacterial cells.ResultsThe GEM-based biosensor cells indicated the reporter gene expression in the presence of Cd2+, Zn2+ and Pb2+ either singly or in combination. Further, the same biosensor cells calibrated for fluorescent intensity against heavy metal concentration generated linear graphs for Cd2+, Zn2+ and Pb2+ with the R2 values of 0.9809, 0.9761 and 0.9758, respectively as compared to non-specific metals, Fe3+ (0.0373), AsO43− (0.3825) and Ni2+ (0.8498) making our biosensor suitable for the detection of low concentration of the former metal ions in the range of 1–6 ppb. Furthermore, the GEM based biosensor cells were growing naturally within the concentration range of heavy metals, at 37 °C and optimum pH = 7.0 in the medium, resembling the characteristics of wildtype E.coli.ConclusionFinally, the novel GEM based biosensor cells developed in this study can be applied for detection of targeted heavy metals in low concentration ranges (1–6 ppb) at normal bacterial physiological conditions.

Hybrid CMOS and Pseudo-CMOS Organic Memory for Flexible Sensors

In this paper, we propose and elucidate a novel static random access memory (SRAM) for flexible electronic systems using low-voltage organic thin-film transistors. The SRAM can be used for local data storage and post-processing of the signals generated by sensors. This is essential for truly flexible systems. The proposed SRAM utilizes hybrid CMOS and pseudo-CMOS design to enhance stability. The memory cells based on CMOS design style utilize p-type access transistors to improve area efficiency and stability. A degradation-mitigation circuit, based on pseudo-CMOS design style, extends retention time. The proposed circuit, which is comprised of few basic logic gates, is easy to implement and occupies minimum layout area. The SRAM circuit can self-detect degradation and automatically perform a process to mitigate device degradation at the necessary time periods.We confirm the operation of key components in the proposed memory via test chip measurements. Additionally, the effectiveness of the degradation-mitigation circuit has been verified.

Ternary combinational logic gate design based on tri-valued memristors

Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring. In contrast to the binary logic circuit design in this method, ternary combinational logic circuit implementation is more complicated. In this paper, a ternary circuit design method that does not require cascading basic ternary logic gates is proposed based on a tri-valued memristor, which can directly realize specific logic functions through a series connection of memristors. The ternary encoder, ternary decoder, ternary comparator, and ternary data selector are implemented by this method, and the effectiveness of the circuits is verified by LTspice simulations.

Research and application of Big data encryption technology based on quantum lightweight image encryption

Given the limitations of current classic image encryption algorithms and the unconditional security characteristics of quantum key distribution protocols, the author proposes an image encryption method based on quantum key distribution and pixel scrambling. The author first analyzed the security issues of quantum image encryption algorithms based on image scrambling methods, namely that image scrambling methods have periodicity, which can ensure that the image can be restored after scrambling. If an image cannot be guaranteed to return to its original state after performing scrambling operations, legitimate users cannot obtain the secret information in the original image, and image scrambling loses its original meaning; However, the periodicity of image scrambling methods not only ensures that legitimate users can decrypt images, but also provides convenience for attackers to steal original image information. Secondly, it is pointed out that when evaluating and analyzing quantum image encryption algorithms, the evaluation indicators should include two parts: One is performance analysis, which is the analysis of the network complexity of quantum circuits. In quantum computing, the network complexity of quantum circuits is usually represented by the number of quantum basic logic gates. The second is security analysis, which mainly includes key analysis (including key space size and key sensitivity analysis), statistical analysis (including pixel correlation, histogram analysis, information fusion, and scatter plot distribution density analysis). Finally, experimental simulations have shown that the NPCR values of the plaintext and ciphertext images of the three images tend to 100%. The encrypted image histogram is evenly distributed, with very weak pixel correlation and high pixel change rate and information entropy.

Role of Flow Cytometry in the Diagnosis of Chronic Myeloid Leukemia

To analyze the immunological phenotype of chronic myeloid leukemia (CML), and explore its characteristics and significance. The immunophenotypes of 40 CML children and 40 controls were analyzed by multicolor flow cytometry. CD45/SSC, as the basic gate, was used to delineate neutrophils. Then, the distribution of cluster differentiation (CD) molecules on the surface of granulocytes was analyzed in three ranges (≥1%, ≥5%, and ≥20%), and the expression rates of CD molecules (≥1% included in the statistical analysis) and the mean fluorescence intensity (MFI) were compared between the two groups. The proportion of granulocytes in the CML group was (82.1±6.4)%, which was significantly higher than (57.8±11.8)% in the control group (P <0.001). The expression rates of CD15/CD11b/CD33/CD13 in CML and control groups were high, and both distributed in the range of ≥20%. The differentiation trajectory of CD33/CD13 was normal and there were no significant differences in the expression rate and MFI between the two groups. However, both the expression rate of CD11b and CD15 MFI in the CML group were significantly lower than those in the control group (P <0.001). There were no significant differences in the expression rate and MFI of CD10 between the two groups, and the expression levels of CD10 between the two groups were consistent in different distributions. In the CML group, there was a large number of cases with abnormal high expression of CD56, 52.5% of the cases had a CD56 expression rate of ≥5%, and 42.5% had a CD56 expression rate of ≥20%, while the control group did not express CD56 (<1%). The expression distribution of CD117 was different between the two groups. In the range of expression rate ≥5%, there were 35.0% cases in the CML group, while only 2.5% in the control group. The expression rate of CD117 in the CML group was higher than that in the control group (P <0.001), though there was no significant difference in MFI. The immunophenotyping of CML is characterized by increased proportion of mature neutrophils, decreased CD15 MFI, decreased proportion of CD11b and abnormal high expression of CD56 and CD117. Flow cytometric analysis of immunophenotype can effectively distinguish normal granulocytes from chronic granulocytes, and help in the diagnosis of CML.

Design Method of Meta Operators Based on Equivalence Class Distribution

Currently, there are many physical systems for quantum computing and to adapt to the physical characteristics of different systems, engineers have designed different basic gate groups for gate circuit calculation models. The quantum algorithm realizes the evolution of the quantum state by applying unitary operators to the quantum states, and the results are obtained by measuring the outputs. These operators will be done in the corresponding physical system by compiling and decomposing into hardware supported basic gates. Universal fundamental gates can construct all quantum algorithms, but their computational efficiency is limited. Drawing on the idea of meta operators in classical machine learning, by constructing a deep learning framework for deep learning models, the common computational logic of operators in different deep learning frameworks is abstracted as ‘meta operators’ [1, 2]. This article aims to study and propose the common computational logic of quantum computing with geometric equivalence class distribution methods, using the volume size of the equivalence class space as a performance indicator for meta operators and identifying the optimal meta operators to optimize the depth of the circuits in the experiments. Which proves the effectiveness of the design method proposed and provides solutions for quantum circuit optimization and dedicated gate design.

Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular. Out of numerous ternary logic devices, carbon nanotube (CNT) FET (CNTFET) is considered a good candidate over silicon FETs. Hence, in this study, ternary schematics are developed based on Pseudo N-type CNTFETs. The ternary basic designs such as standard ternary inverter (STI), AND and OR gates are presented. Then, using the proposed basic logic gates, the complex designs such as full adder and full subtractor are also proposed. The HSPICE simulator is utilized to design proposed circuits and analyze different performance parameters. The performance such as delay, power and power delay product (PDP) are analyzed for the proposed circuits. Moreover, the proposed schematics performances are also compared to complementary schematics. It investigated that Pseudo N-type CNTFET schematics improved the overall performance on an average up to 65.82% over the complementary ternary circuits.

Design of the Clockless Logic Gates Based on Quantum Phase Slip Junction

In this manuscript, clockless circuits of the two basic logic gates, namely AND and OR gates are designed by using the quantum phase slip junction (QPSJ). In the previously designed (existing) circuits of these gates, there is an internal clock pulse source in the output branch which is necessary for proper gate operation. When the existing AND and OR gates have to be connected to another gate, this internal clock pulse becomes in series between their outputs and the input of the next gate. As the result, the internal clock pulse must be provided by a separate source from, but synchronized to the system clock pulse (which is needed for synchronization of the inputs). This increases the design complexity. By using the proposed clockless AND and OR gates, the mentioned design complexity is removed. In addition, the proposed clockless gates have less number of QPSJs than the existing ones which allows less occupied area on the chip, higher operation frequency and smaller dynamic power dissipation.

Design of Multiplexers using Reversible Logic Technique

Reversible logic is promising as it can be applied to different applications in low power like nanocomputing especially in quantum computing. Reversible logic is a technioue for power reduction. Reversible circuits are similar to digital circuits but they work using reversible logic gates. This study focuses on reducing the garbage output and ancilla inputs in reversible multiplexers, thereby reducing the power consumption. In this study two designs of Multiplexers are given. Design1 is using TwinSJ gate and AJ gate. 2:1, 4:1 and 8:1 multiplexers are built. In Design 2, a new gate (SJ gate) is built which functions as 2:1 multiplexer. It has 4*4 configuration. The inputs are suitably configured so that it performs various logic functions. Using this SJ gate and other basic reversible logic gates, 2:1, 4:1 and 8:1 multiplexers are built. In 2:1 multiplexer, Ancilla inputs are improved to '0' from 5 and garbage output has been reduced to 2 against 7 in existing design. 4:1 multiplexers are built with ‘0’ ancilla inputs against 2 and 11 in existing designs. Garbage output of the proposed 4:1 multiplexer is 5 against 6 and 16 in existing designs. 8:1 multiplexer is built with 1 ancilla input and 11 garbage output against 2 and 12 respectively in existing design. This is designed using VHDL code - xilinx 14.7 for verification purpose and simulated on ISIM.

Design and analysis of all-optical half and full adder/subtractor using nonlinear asymmetric directional couplers

The utilization of nonlinear asymmetric directional couplers has emerged as a viable alternative to conventional systems for the execution of arithmetic operations using optical signals. The present study explores the utilization of a coupler-based framework for the development of an all-optical half- and full-adder/subtractor circuit designed with the basic logic gates (AND, OR, XOR) and a soliton pulse as input signals. Nonlinear asymmetric directional couplers have been analysed theoretically and numerically, including the detailed mathematics of coupled wave theory. The switching characteristics of XPM effect based All-optical directional couplers have been examined for appropriate values of the phase shift (∆φ). Appropriate values of ∆φ, extinction ratio (dB), and corresponding controlled pump signal levels and other parameters are investigated for an efficient generation of fundamental logic gates. Further, the detailed analysis of layout generation and design aspects of an all-optical half- and full-adder/subtractor circuit along with the basic logic gates circuits has been carried out. Simulation results are validated with the standard result. The research findings demonstrate that soliton pulses might potentially be useful for optical computing applications when used as the input signal to nonlinear asymmetrical directional couplers.