Novel crosstalk circuit design for high density logic applications

Abstract

As IC transistors scale down further, physical limitations are restricting performance growth. The contradiction between demands for computing capabilities and challenges in transistor downscaling is exacerbating. This paper proposed a crosstalk circuit design using interconnect coupling capacitance to improve the computing power of chips. Firstly, a valid model of coupling capacitance between metal interconnects is established based on analysis of the factors affecting coupling capacitance. Then, basic crosstalk gates including NAND and NOR are designed by adopting line crosstalk and sampling inverters. Furthermore, complex logic gates and combination circuits are implemented by using the basic crosstalk gates. For verification, a test chip based on line computing is fabricated in 65 nm CMOS technology and the core area is ∼0.019 mm2. The experimental results verified the correctness of the proposed crosstalk gate's logic. Compared with standard logic circuit, the crosstalk NAND or NOR gates reduce the area overhead by 10.6 % and also enhance the circuit's capability of anti-reverse engineering.