Design of the Clockless Logic Gates Based on Quantum Phase Slip Junction

Abstract

In this manuscript, clockless circuits of the two basic logic gates, namely AND and OR gates are designed by using the quantum phase slip junction (QPSJ). In the previously designed (existing) circuits of these gates, there is an internal clock pulse source in the output branch which is necessary for proper gate operation. When the existing AND and OR gates have to be connected to another gate, this internal clock pulse becomes in series between their outputs and the input of the next gate. As the result, the internal clock pulse must be provided by a separate source from, but synchronized to the system clock pulse (which is needed for synchronization of the inputs). This increases the design complexity. By using the proposed clockless AND and OR gates, the mentioned design complexity is removed. In addition, the proposed clockless gates have less number of QPSJs than the existing ones which allows less occupied area on the chip, higher operation frequency and smaller dynamic power dissipation.