Barrier Lowering Effect Research Articles

Additivity of Diene Substituent Gibbs Free Energy Contributions for Diels-Alder Reactions between (F3C)2B = NMe2 and Substituted Cyclopentadienes.

Systematic computational studies of pericyclic Diels-Alder-type reactions between aminoborane (F3C)2B = N(CH3)2, 1, and all permutations of substituted cyclopentadienes c-C5R1R2R3R4R5aR5b (R = H, CH3, CF3, F) allow isolation of substitutional effects on Gibbs free energy barrier heights and reaction Gibbs free energies. The effects appear to be additive in all cases. Substitution at positions 5a and 5b always increases barriers and reaction energies, an effect explained by steric interactions between substituents and the aminoborane moiety. For cases R = CH3, regioselectivities differ from those expected from canonical organic chemistry predictions. Frontier molecular orbital calculations suggest this arises from the extreme polarization of the π interaction in 1. For cases R = CF3, the 2/3-substitution comparison accords with canon, but the 1/4-substitution comparison does not. This appears to arise from a combination of electronic and steric issues. For cases R = F, many of the reactions are exergonic, in contrast to the cases R = CH3, CF3. Additionally, fluorine substitution at positions 2 and 4 has a barrier-lowering effect. Frontier molecular orbital calculations support an orbital-based preference for formation of 2- and 4-substituted "meta" products rather than "ortho/para" products.

What Is the Catalytic Mechanism of Enzymatic Histone N-Methyl Arginine Demethylation and Can It Be Influenced by an External Electric Field?

Arginine methylation is an important mechanism of epigenetic regulation. Some Fe(II) and 2-oxoglutarate dependent Jumonji-C (JmjC) Nϵ-methyl lysine histone demethylases also have N-methyl arginine demethylase activity. We report combined molecular dynamic (MD) and Quantum Mechanical/Molecular Mechanical (QM/MM) studies on the mechanism of N-methyl arginine demethylation by human KDM4E and compare the results with those reported for N-methyl lysine demethylation by KDM4A. At the KDM4E active site, Glu191, Asn291, and Ser197 form a conserved scaffold that restricts substrate dynamics; substrate binding is also mediated by an out of active site hydrogen-bond between the substrate Ser1 and Tyr178. The calculations imply that in either C-H or N-H potential bond cleaving pathways for hydrogen atom transfer (HAT) during N-methyl arginine demethylation, electron transfer occurs via a σ-channel; the transition state for the N-H pathway is ∼10 kcal/mol higher than for the C-H pathway due to the higher bond dissociation energy of the N-H bond. The results of applying external electric fields (EEFs) reveal EEFs with positive field strengths parallel to the Fe=O bond have a significant barrier-lowering effect on the C-H pathway, by contrast, such EEFs inhibit the N-H activation rate. The overall results imply that KDM4 catalyzed N-methyl arginine demethylation and N-methyl lysine demethylation occur via similar C-H abstraction and rebound mechanisms leading to methyl group hydroxylation, though there are differences in the interactions leading to productive binding of intermediates.

Comparative Analysis of FINFETS and MOSFETS

This paper makes a brief introduction of CMOS technology and illustrates the structure of traditional MOSFETs and Fin-FETs and their developing process. To help better understand advantages and drawbacks of both two technologies, it also explains the Drain Induced Barrier Lowering (DIBL) effect and its impact on transistor performance. The paper compares the DIBL ratio of Double-Gate Fin-FETs and Double-Gate MOSFETs by varying channel length using Fin-FET and MOSFET in similar structural parameters. The results are shown in different diagrams, which proves that Fin-FETs have a better control of DIBL effect than conventional MOSFETs. In the end it explains the shortcomings of the experiment and describes future expectations for Fin-FET technology.

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N+ pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N+ SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N+ pocket structure was higher than that of the N+ SiGe pocket, but at high drain voltages, the order was reversed.

Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors

In this study, the negative drain-induced barrier lowering (DIBL) and negative differential resistance (NDR) effects are investigated in detail in negative-capacitance field-effect transistors (NCFETs) with a fully depleted silicon-on-insulator structure. We show that the negative DIBL and NDR effects are caused by a decrease in the internal gate voltage, which is closely related to the matching between the ferroelectric capacitance and the total gate capacitance of the underlying FET. Further, we define the remnant-polarization-to-coercive-field ratio (RPE), which can be directly used as a parameter to quantify the DIBL effect and describe the sign of the NDR effect. DIBL tends to be consistent with the same RPE, despite exhibiting different current intensities in the strong inversion region. With regard to different RPE, the DIBL effect decreases but the NDR effect increases as RPE decreases. Our work may provide further insight for NCFET designers to adjust capacitance matching to optimize the DIBL and NDR effects.

Self-induced ferroelectric 2-nm-thick Ge-doped HfO2 thin film applied to Ge nanowire ferroelectric gate-all-around field-effect transistor

This paper reports a self-induced ferroelectric 2-nm-thick Ge-doped HfO2 (Ge:HfO2) thin film. Ge thermal desorption, incorporation into HfO2, and further Ge:HfO2 crystallization were all performed through rapid thermal annealing simultaneously. The ferroelectric property of a 2-nm-thick Ge:HfO2/2-nm-thick Al2O3 dielectric stack was confirmed using the polarization-electric field measurement. X-ray photoelectron spectroscopy was used to confirm that Ge bonded to HfO2 as Hf-germanates. Piezoresponse force microscopy was used to demonstrate the piezoelectric property of Ge:HfO2/Al2O3. Furthermore, a dielectric stack of Ge:HfO2/Al2O3 was applied as a gate insulator in a Ge nanowire gate-all-around ferroelectric field-effect transistor (Ge NW Fe-GAAFET). The device exhibited a minimum steep-sub-threshold slope of 47 mV/dec, a high ION/IOFF ratio of >106, and low gate leakage current; moreover, it was free of a drain-induced barrier lowering effect. The proposed self-induced ferroelectric Ge:HfO2 Ge NW Fe-GAAFET is feasible for future ultra-low power integrated circuit applications.

Impact of Selective Epitaxial Growth and Uniaxial/Biaxial Strain on DIBL Effect Using Triple Gate FinFETs

The influence of Selective Epitaxial Growth (SEG) and the Uniaxial and Biaxial Strain are studied in triple gate FinFETs, analyzing the Drain Induced Barrier Lowering Effect (DIBL). The splits using SEG present better performance for strained devices than the unstrained ones but the inverse is observed for devices without SEG. The DIBL values are higher for SEG devices in all cases. For devices without SEG, the effect of mechanical stress is more pronounced and the mobility is higher in the uniaxially strained devices. These devices have lower VT values in the saturation condition causing the highest DIBL.

Investigation of tied double gate 4H–SiC junctionless FET in 7 nm channel length with a symmetrical dual p+ layer

In this work, we present a novel ultra-thin 4H–SiC junctionless tied double gate field effect (DG-JLFET) transistors with a symmetrical dual p + layer (S-D-P DG-JLFET) and the proposed structure compared with a conventional junctionless tied double gate field effect structure (DG-JLFET). By changing the depletion region in the proposed structure and due to the symmetrical dual p + layer, off-current and drain induced barrier lowering (DIBL) effect is improved but on-current reduces a bit. In our paper, we discuss the work function effect on the off and on-current. Also, the effects of temperature on the electron mobility, the threshold voltage, and changing the lengths of the added p + layers have been investigated. Due to the design complexity of the devices in sub 20-nm, the proper models are considered. The ratio of the I on /I off current of the proposed structure improves significantly versus the conventional double gate junctionless FET. • Improvement in properties of semiconductor physique. • Improvement of control on carrier concentration by gate electrode. • Enhancement of depletion region and better leakage current.

Analytical Modeling of Threshold Voltage for Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET

This paper presents, analytical modeling of surface potential,threshold voltage and DIBL for a Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET considering the parabolic approximation of surface potential. Poisson’s three-dimensional (3D) charge density equation has been solved by using proper boundary conditions to formulate the surface potential throughout the channel length. In this work, two gate metals of distinct work functions are used for gate electrode to create a step profile in channel potential. The potential step profile in surface potential reduces the SCEs in DM-DG-GAA MOSFET. The developed surface potential model is further considered to formulate the threshold voltage (Vth)model by using an effective conductive path and Fermi potential difference. The modeled threshold voltage is further used to find the Drain Induced Barrier Lowering (DIBL) effect. The threshold voltage and the DIBL are discussed with different values of device physical parameters like gate oxide (sio2) thickness, gate length ratio, channel thickness, and screening gate work function. This paper compares the SCEs of DM-DG-GAA MOSFET with Dual-Gate Gate-All-Around (DG-GAA) MOSFET and the results showing that DM-DG-GAA MOSFET offering better short channel characteristics than DG-GAA MOSFET. The model results are verified with simulation results generated from 3D device simulator ATLAS from SILVACO.

Analytical Model for Drain Current of a Ballistic MOSFET

A simplified analytical approach within the framework of Landauer-Buttiker formalism has been employed to model the drain current in a ballistic n-channel metal oxide semiconductor field effect transistor (MOSFET) and the expression for the device threshold voltage has been obtained. To achieve ballistic operation the said MOSFET has been modeled considering low temperature (77 K) and intrinsic silicon channel for electronic motion of the charge carriers. The model incorporates quantum confinement effect, drain induced barrier lowering (DIBL) and short channel effects (SCE). Further, the effects due to surface scattering and back scattering are included in this model to obtain a near ballistic behavior. The current-voltage characteristics are compared with the available experimental results and are found to be in reasonable agreement.

Few-Layered MoS2 Field-Effect Transistors with a Vertical Channel of Sub-10 nm.

Few-layered molybdenum disulfide (MoS2) has demonstrated promising advantages for the integration of next-generation electronic devices. A vertical short-channel MoS2 transistor with a channel length of sub-10 nm can be realized using mica as the insulated mesa and MoS2 flake dry-transferred onto the mica as the channel. A near-perfect symmetrical and fully saturated output characteristic can be obtained for the positive or negative drain-source voltage. This result is attributed to an effective transformation of the drain-source electrode contact from Schottky contact to Ohmic contact via forming gas annealing. The vertical-channel MoS2 transistor with a channel length of 8.7 nm exhibits excellent electrical characteristics, for example, a negligible hysteresis voltage of 60 mV, an extraordinarily small subthreshold swing of 73 mV/dec, a considerably weakened drain-induced barrier-lowering effect (100 mV/V), and the first-reported intrinsic delay time of 2.85 ps. Moreover, a logic inverter can be realized using the two vertical-channel MoS2 transistors, with a high voltage gain of 33. Experimental results indicate that the developed method is a potential approach for fabricating MoS2 transistors with an ultrashort channel and high performance, and consequently, manufacturing MoS2-based integrated circuits.

Nanowire gate-all-around MOSFETs modeling: ballistic transport incorporating the source-to-drain tunneling

Incorporating the source-to-drain tunneling current that is valid in all operating regions, an analytical compact model is proposed in this paper for cylindrical ballistic gate-all-around n-type metal-oxide-semiconductor field-effect transistors with ultra-short silicon channel. From taking the drain-induced barrier lowering effect into consideration, the potential distribution within the device channel has been modeled based upon a 2D analysis in our previous work. In this study, by introducing a parabolic function when modeling the potential profile in the channel direction, we found out that the source-to-drain tunneling effect in the subthreshold region could be evaluated analytically by applying Wentzel–Kramers–Brillouin approximation. Then, it is practical to estimate the ballistic drain current for all operating regions analytically with this compact model considering both the source-to-drain tunneling and thermionic transport. The resulting analytic compact model is tested against non-equilibrium Green's function simulation using SILVACO, and good accuracy is demonstrated. Finally, we perform an NMOS inverter circuit simulation using HSPICE, when introducing our model to it as a Verilog-A script.

Enhancement of Short Channel Effect and Drain Induced Barrier Lowering in Fin-FET

The essential requirement of any battery-operated and mobile devices like laptops, cellular phones are that they must be small in size, consume less power, fast processing and cheaper expansion. Gordon Moore found in 1965 that the quantity of transistors on a chip will drive to be twofold every year, by manufacturing the portable devices and building circuit on the silicon chip which makes device cost effective. This drop in size of transistor is termed as scaling. Since scaling faces formidable challenges in nanometer regime, successors have been emerged as FinFET’s. They have thin fin or wing like channels enclosed by several gates. Due to many gates the design helps to improve performance and boost energy efficacy. Present work highlights the role of scaling and how scaling improves the speed of the device. The expectation from the scaled device is to consume as low power as possible, effective in costs and less design time. As we make the instrument more portable, complexity in it becomes infinite. Moore’s law supports us to realize the role of scaling to improve circuit performance and make a portable/mobile device. Here, we design 14nm, 10nm and 7nm Triple gate Fin-FET (TG Fin-FET) and investigate the Drain Induced Barrier Lowering (DIBL) and Short Channel Effect (SCE). By scaling the device DIBL and SCE are reduced giving better performance in terms of power and speed.

Modeling of the temperature effects in filamentary-type resistive switching memories using quantum point-contact theory

Electron transport in filamentary-type resistive switching memories is modeled using quantum point-contact theory. The filament is represented by a parabolic-shaped tube-like constriction in which the first quantized subband behaves as a one-dimensional tunneling barrier. Computation of the current flowing through the atomic-sized structure is carried out by means of the finite-bias Landauer approach. Different approximations for the barrier transmission coefficient are assessed with the aim of determining the role played by the temperature of the charge reservoirs. In order to corroborate the proposed model, current-voltage measurements in electroformed Ni/HfO2/Si devices operating in the non-linear transport regime were performed in the temperature range from −40 C to 200 C. Obtained results using inverse modeling indicate that a temperature-induced barrier lowering effect explains the experimental observations. Finally, the model proposed to calculate the device current including the temperature dependence is developed.

Mechanism of Reverse Leakage Current in Schottky Diode Fabricated on Large Bandgap Semiconductors like Ga2O3 or Diamond

The bandgap of Ga2O3 (4.5-4.9 eV) is larger than the bandgap of GaN (3.4 eV). In addition, single crystal bulk Ga2O3 wafers can be more easily manufactured than GaN wafers. Therefore, Ga2O3 has strong potential for applications in high power semiconductor devices [1]. Schottky diodes fabricated on n-type Ga2O3 have strong potential as fast high-power switching devices. Similarly, the bandgap of diamond (5.5 eV) is very large and diamond Schottky diodes have good potential.For example, Harada et al. published their work on Schottky diodes fabricated on n-type Ga2O3 with PdCoO2 as the metal [2]. They claimed that their Schottky diodes have a very large Schottky barrier height of 1.8 eV. Other scientists using metals like W, Au, Ir, Pd or Pt cannot achieve such a large value of the Schottky barrier height. However, they did not propose any physical mechanism regarding the reverse leakage current in their Schottky diodes. One possible mechanism of reverse leakage current in Schottky diodes fabricated on n-type Ga2O3 is image force barrier lowering at the metal-Ga2O3 interface. Historically, there were 2 theories regarding the image force barrier lowering effect. In 1953, Krömer published his theory that the image force dielectric constant in the equation for Schottky emission should be equal to 1 [3]. Subsequently in 1964, Sze et al. published their theory that the image force dielectric constant in the equation for Schottky emission should be equal to n2 [4], where n is the refractive index of the semiconductor in the infrared or visible light range. The theory of Sze et al. quickly became the dominating theory whereas Krömer’s theory essentially became a forgotten theory. For Ga2O3, n is approximately equal to 2 [5] and so n2 is about 4. The author performed an analysis on the experimental data published by Harada et al. [2] and found that Krömer’s theory fit the experimental data from Harada et al. much better than the theory of Sze et al. Similarly, the author noticed that Krömer’s theory is better than the theory of Sze et al. for diamond Schottky diodes.In conclusion, the author pointed out that it is necessary to resurrect an old and forgotten theory from Krömer in order to explain the experimental data on the reverse leakage current of Schottky diodes fabricated on large bandgap semiconductors like Ga2O3 and diamond.

Mechanism of Reverse Leakage Current in Schottky Diode Fabricated on Large Bandgap Semiconductors like Ga2O3 or Diamond

One possible mechanism of reverse leakage current in Schottky diodes fabricated on large bandgap semiconductors like Ga2O3 or diamond is Schottky emission (image force barrier lowering) at the metal-semiconductor interface. Historically, there were 2 theories regarding the image force barrier lowering effect. The author’s new idea is that the older and almost forgotten Krömer’s theory can frequently give a much better fit to experimental data for large bandgap semiconductors like Ga2O3 or diamond Schottky diodes. It is possible to define an effective dielectric constant Keff in the reverse leakage current equation and quite frequently 1 ≥ Keff ≥ ¼ for some large bandgap semiconductors like Ga2O3 or diamond. Peripheral surface passivation is important.

Modeling of Surface Potential and Fringe Capacitance of Selective Buried Oxide Junctionless Transistor

The Selective Buried Oxide-Charge Plasma based Junctionless Transistor (SELBOX-CPJLT) is a new upcoming device used mainly for reducing self-heating effects and second order effects. In this paper, 2D mathematical modeling of Surface Potential for SELBOX-CPJLT using Poisson’s equation has been proposed. We have modelled the fringe capacitance for SELBOX-CPJLT with the help of conformal mapping. SELBOX structure is a novel idea to counter the self-heating effect which is present in the SOI technologies. Implementation of the charge plasma on SELBOX based JLT MOSFETs is called as SELBOX-CPJLT. The electrostatic performance and the lattice temperature of SELBOX-CPJLT is also compared with the SELBOX-JLT in this paper. The simulation results show that the SELBOX-CPJLT device has low Drain Induce Barrier Lowering (DIBL) effect, Subthreshold Slope (SS) with high Ion/Ioff ratio. It also provides good thermal stability as compared to SELBOX-JLT. The Fringe capacitance of SELBOX-CPJLT MOSFET has also been tabulated for different device parameters using conformal mapping technique. The proposed device is simulated and validated by using 2D-Silvaco (ATLAS) simulation.

Metal–Semiconductor–Metal ε-Ga2O3 Solar-Blind Photodetectors with a Record-High Responsivity Rejection Ratio and Their Gain Mechanism

In recent years, Ga2O3 solar-blind photodetectors (SBPDs) have received great attention for their potential applications in solar-blind imaging, deep space exploration, confidential space communication, etc. In this work, we demonstrated an ultra-high-performance ε-Ga2O3 metal–semiconductor–metal (MSM) SBPD. The fabricated photodetectors exhibited a record-high responsivity and fast decay time of 230 A/W and 24 ms, respectively, compared with MSM-structured Ga2O3 photodetectors reported to date. Additionally, the ε-Ga2O3 MSM SBPD presents an ultrahigh detectivity of 1.2 × 1015 Jones with a low dark current of 23.5 pA under an operation voltage of 6 V, suggesting its strong capability of detecting an ultraweak signal. The high sensitivity and wavelength selectivity of the photodetector were further confirmed by the record-high responsivity rejection ratio (R250 nm/R400 nm) of 1.2 × 105. From the temperature-dependent electrical characteristics in the dark, the thermionic field emission and Poole–Frenkel emission were found to be responsible for the current transport in the low and high electric field regimes, respectively. In addition, the gain mechanism was revealed by the Schottky barrier lowering effect due to the defect states at the interface of the metal contact and Ga2O3 or in the bulk of Ga2O3 based on current transport mechanism and density functional theory calculations. These results facilitate a better understanding of ε-Ga2O3 photoelectronic devices and provide possible guidance for promoting their performance in future solar-blind detection applications.

Effects of Applied Voltages on the Charge Transport Properties in a ZnO Nanowire Field Effect Transistor.

We investigate the effect of applied gate and drain voltages on the charge transport properties in a zinc oxide (ZnO) nanowire field effect transistor (FET) through temperature- and voltage-dependent measurements. Since the FET based on nanowires is one of the fundamental building blocks in potential nanoelectronic applications, it is important to understand the transport properties relevant to the variation in electrically applied parameters for devices based on nanowires with a large surface-to-volume ratio. In this work, the threshold voltage shift due to a drain-induced barrier-lowering (DIBL) effect was observed using a Y-function method. From temperature-dependent current-voltage (I-V) analyses of the fabricated ZnO nanowire FET, it is found that space charge-limited conduction (SCLC) mechanism is dominant at low temperatures and low voltages; in particular, variable-range hopping dominates the conduction in the temperature regime from 4 to 100 K, whereas in the high-temperature regime (150–300 K), the thermal activation transport is dominant, diminishing the SCLC effect. These results are discussed and explained in terms of the exponential distribution and applied voltage-induced variation in the charge trap states at the band edge.