Modeling of Surface Potential and Fringe Capacitance of Selective Buried Oxide Junctionless Transistor

Abstract

The Selective Buried Oxide-Charge Plasma based Junctionless Transistor (SELBOX-CPJLT) is a new upcoming device used mainly for reducing self-heating effects and second order effects. In this paper, 2D mathematical modeling of Surface Potential for SELBOX-CPJLT using Poisson’s equation has been proposed. We have modelled the fringe capacitance for SELBOX-CPJLT with the help of conformal mapping. SELBOX structure is a novel idea to counter the self-heating effect which is present in the SOI technologies. Implementation of the charge plasma on SELBOX based JLT MOSFETs is called as SELBOX-CPJLT. The electrostatic performance and the lattice temperature of SELBOX-CPJLT is also compared with the SELBOX-JLT in this paper. The simulation results show that the SELBOX-CPJLT device has low Drain Induce Barrier Lowering (DIBL) effect, Subthreshold Slope (SS) with high Ion/Ioff ratio. It also provides good thermal stability as compared to SELBOX-JLT. The Fringe capacitance of SELBOX-CPJLT MOSFET has also been tabulated for different device parameters using conformal mapping technique. The proposed device is simulated and validated by using 2D-Silvaco (ATLAS) simulation.