Band-to-band Tunneling Research Articles

Line-tunneling based GaP/Si heterostructure vertical gate-all-around tunnel FET for enhanced electrical performance

This study explores strategies to enhance Tunnel FET performance through innovative device geometry and heterostructure integration. The use of a GaP/Si heterostructure, combined with a heavily doped n + source pocket, significantly boosts BTBT (band-to-band tunneling). The gate, which completely surrounds the source, induces line-tunneling and improves gate control over the tunnel junction, further contributing to enhanced device performance. The incorporation of a gate-drain underlap architecture and a vertically oriented design effectively suppresses ambipolar and leakage currents, resulting in an increased current ratio, reduced subthreshold slope (SS), and a minimized device footprint. Comparative analysis with existing TFET architectures shows that the optimized device achieves promising results, including an average SS of 13 mV/decade, an off-current (Ioff) of 2.36 × 10-17 A, an on-current (Ion) of 2.1 × 10-5 A, and an ambipolar current (Iamb) of 3.28 × 10-16 A.

Performance assessment of SiGe extended four corner source TFET for biosensing applications

In this paper, the performance of a novel SiGe extended four corner source tunneling field–effect transistor (SiGe EFCS TFET) based dielectrically modulated label-free biosensor has been investigated for biosensing applications. Using a combination of heterostructure (SiGe/Si) and extended four corner source (EFCS) lead to increased band–to–band tunneling (BTBT) probability, improved gate control and superior drain current sensitivity for biomolecule conjugation in comparison with a conventional TFET and Si EFCS TFET structures of similar dimensions. The influence of both the charge–neutral and charged biomolecules on the sensitivity performance is investigated using the Silvaco TCAD ATLAS semiconductor device simulator with a calibrated nonlocal BTBT model. Four different kinds of biomolecules such as Streptavidin, Ferro–cytochrome c, Keratin and Gelatin with various charge density values were used for this purpose. In order to model steric hindrance effects in partially filled cavities, in addition to various fill factors, four different step profile patterns have considered such as convex, concave, decreasing and increasing step profiles. Also, the dependence of the nanogap cavity properties on the sensing performance in terms of the length and thickness is investigated. A maximum drain current sensitivity of 1.69 × 105 is achieved in SiGe EFCS TFET for Gelatin biomolecules in a fully filled nanogap cavity at overdrive and drain voltages of 0.5 V.

New tunneling source follower with low 1/f noise and high voltage gain

We have designed a tunneling source follower (TSF) for image sensors that achieves high voltage gain (Av) and low 1/f noise simultaneously. The TSF is composed of N-P-N-N, especially the p-doped grounded area, which serves to amplify the insufficient tunneling current, allowing the source follower (SF) to utilize band-to-band tunneling (BTBT). Compared to thermionic emission, tunneling based structures contribute to increasing Av through lower channel length modulation and lower body effect. As a result, TSF achieves a higher Av (~ 1.0 V/V) than conventional SF (~ 0.9 V/V). Moreover, the n-doped channel makes the buried conductive channel farther from the interface, lowering the noise. The input-referred voltage noise spectral density (SV) is approximately 10 times lower in TSF than that of in conventional SF. Therefore, our TSF can be a possible candidate for High Av and low 1/f noise image sensors.

Steep subthreshold swing Double - Gate tunnel FET using source pocket engineering: Design guidelines

In this work, we propose a promising source engineered Double - Gate (DG) Tunnel Field Effect Transistor (TFET) device capable of providing remarkably low value of Subthreshold Swing (SS) with sufficiently high drive current. Using Sentaurus TCAD simulations, we demonstrate that counter-doped horizontal pockets (doping of pocket is kept opposite to that of source) when placed in the source region introduces a built-in band bending at the source-pocket junction. This lowers the minima of Conduction Band (CB) in pocket region thereby reducing the barrier width as the pocket CB moves closer to source Valence Band (VB). As a result, stronger electric field is observed thereby reducing the threshold voltage (onset of band-to-band tunneling (BTBT)) and subsequent reduction in subthreshold swing. To boost the ON-current and suppress ambipolarity, high-k dielectric material along with low work-function gate material is introduced at source side and low-k gate dielectric along with high work-function gate material is introduced at drain side. Compared to point tunneling in conventional TFETs, the gate overlapped pockets in the proposed structure result in an increase in cross-section area available for BTBT thereby leading to line tunneling of carriers from the source to the pocket, resulting in higher ON-current. In this work, we discuss the role of source engineering in boosting the performance of Hetero-Dielectric (HD) Dual-Metal-Double-Gate (DMDG) TFET. We provide design guidelines to achieve steeper subthreshold swing while considering pocket doping and pocket thickness as the key parameters. A comparative study of conventional DG-TFET and HD-DG-TFET with the proposed Gate-over-Pockets (GoP) HD-DMDG-TFET structure is done. When compared to the conventional DG-TFET with same geometrical parameters, the proposed structure provides ∼33× steeper SS, more than two order improved ON-current, two order lower ambipolar current and 133 folds better Ion/Ioff thus becomes the perfect choice for low power applications.

Cutting-edge vertical tunnel FETs: GaSb/InSb heterojunction source-all-around tunnel FET with I60 of 2.73×10⁻⁴ A/μm and Sub-10 mV/dec SS

This work introduces an innovative Source-All-Around Vertical Tunnel Field-Effect Transistor (SAA-VTFET) design based on III-V semiconductors. The unique combination of a GaSb/InSb heterojunction, a wider tunneling space, and an n+ source pocket significantly enhances band-to-band tunneling (BTBT), leading to exceptional on-current levels. The device architecture utilizes InSb in the source pocket and channel, materials chosen for their properties that enable efficient carrier transport, ultimately boosting overall device performance. Through meticulous optimization, the SAA-VTFET achieves an I60 (Ids at SS = 60mV/dec) of 2.73 × 10−4 A/μm, an exceptionally low off-current of 1.7 × 10−17 A/μm, a low threshold voltage of 0.16 V, an outstanding ION/IOFF Ratio of 1.64 × 1013, and an attractive subthreshold swing (point SS of 4 mV/dec, average SS of 7 mV/dec). These remarkable achievements underscore the SAA-VTFET's potential to surpass conventional TFETs, paving the way for advanced low-power, high-speed electronics.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability

In this article, the impact of interface-trap charges (ITCs) on the DC and analog/RF parameters of gate-all-around vertical TFET (GAA-VTFET) are considered to evaluate the reliability of the device. ITCs are included at oxide/semiconductor interface of GAA-VTFET where the probability of occurrence of traps are high owing to faults in the manufacturing process. A detailed investigation is carried out by tuning the temperature, polarities and density of ITCs. It is clearly observed from TCAD based simulation results that the presence of traps alters the flat-band voltage, thereby affecting the overall performance of the device. Transfer characteristics of the device depicts that impact of traps shows more variation in the OFF-state current than the ON-current. However, presence of donor traps improves the analog/RF parameter, such as parasitic capacitances (Cgg), Transconductance (gm), cut-off frequency (fT), output resistance (Rout) etc. Furthermore, the simulation results proclaim that GAA-VTFET shows more resilient to acceptor traps than the positive traps. Moreover, by examining the influence of ambient temperature on device performance, it is revealed that the drain current in the subthreshold region (at low gate bias) is more susceptible to the degradation than the super-threshold region at elevated temperature. This is mainly due to the superiority of the trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) recombination mechanisms over the band-to-band tunneling (BTBT). When the raise in ambient temperature is tuned between minimum of 200 K to maximum of 400 K, it is observed that OFF-current increases by ∼7 times. Lastly, voltage-transfer characteristics (VTC) analysis of the resistive-load inverter clearly demonstrates that the influence of traps on the noise margin is within acceptable limits.

A resilient type-III broken gap Ga2O3/SiC van der Waals heterogeneous bilayer with band-to-band tunneling effect and tunable electronic property

The potential of van der Waals (vdW) heterostructure to incorporate the outstanding features of stacked materials to meet a variety of application requirements has drawn considerable attention. Due to the unique quantum tunneling mechanisms, a type-III broken-gap obtained from vdW heterostructure is a promising design strategy for tunneling field-effect transistors. Herein, a unique Ga2O3/SiC vdW bilayer heterostructure with inherent type-III broken gap band alignment has been revealed through first-principles calculation. The underlying physical mechanism to form the broken gap band alignment is thoroughly studied. Due to the overlapping band structures, a tunneling window of 0.609 eV has been created, which enables the charges to tunnel from the VBM of the SiC layer to the CBM of the Ga2O3 layer and fulfills the required condition for band-to-band tunneling. External electric field and strain can be applied to tailor the electronic behavior of the bilayer heterostructure. Positive external electric field and compressive vertical strain enlarge the tunneling window and enhance the band-to-band tunneling (BTBT) scheme while negative electric field and tensile vertical strain shorten the BTBT window. Under external electric field as well as vertical and biaxial strain, the Ga2O3/SiC vdW hetero-bilayer maintains the type-III band alignment, revealing its capability to tolerate the external electric field and strain with resilience. All these results provide a compelling platform of the Ga2O3/SiC vdW bilayer to design high performance tunneling field effect transistor.

Computational modelling of cylindrical-ferroelectric-dual metal-nanowire field effect transistor (C-FE-DM-NW FET) using landau equation for gate leakage minimization

In order to address and resolve the significant problem of gate-induced drain leakage (GIDL) current and enhance device reliability, band-to-band tunnelling (BTBT), and OFF-state leakages, a computational model of a cylindrical-ferroelectric-dual-metal-nanowire-field effect transistor (C-FE-DM-NW-FET) has been proposed in this manuscript. The proffered structure is a symmetric gate structure with ferroelectric layer sandwiched between the gate terminal and oxide layer which reduces the BTBT which in term reduces the OFF-state leakage hence making the device definitive for low power applications. In this manuscript, there has been a reduction in the leakage current by a magnitude of 104 times in 50 nm and 107 times in 60 nm channel length which translates to a reduction in gate leakage (IGIDL) of more than 100 % in C-FE-NW-FET over C-NW FET. To analyze the Electric Field, Surface Potential, and IGIDL with the proper boundary conditions, the 2D Poisson's equation is solved analytically with Landau-Khalatnikov (LK) equation. The analytical findings are quite similar to the simulated outcomes.

Two-dimensional transition metal dichalcogenides van der Waals heterojunctions with broken-gap for tunnel field-effect transistors applications

The scaling down of transistors is nearing the limits dictated by Moore's Law, primarily due to the quantum tunneling effect. This challenge has spurred considerable interest in exploring novel materials characterized by broken-gap band alignment. Among these materials, two-dimensional (2D) materials-based van der Waals heterojunctions (vdWHs) have emerged as promising candidates, owing to their nanoscale dimensions, which render them suitable for transistor construction. Type-III vdWHs, in particular, have been investigated for their ability to facilitate rapid quantum Band-To-Band Tunneling (BTBT), thereby enabling low-power charge transport. In our study, we conducted a detailed analysis of four vdWHs comprised of HfSe2 and WXY (where X and Y represent Se or Te). Our findings indicate that 2D WSeTe (or WTe2)/HfSe2 vdWHs exhibit a broken-gap band alignment (type-Ⅲ) under the influence of an external electric field, thus showcasing potential for integration into future tunnel field-effect transistors (TFETs). Additionally, our investigation revealed that the band gap of two other vdWHs, WTeSe (or WSe2)/HfSe2, varies linearly with the external electric field, fluctuating between 0.4 eV and 1.0 eV. This characteristic makes them well-suited for application as infrared detectors. By unveiling the distinct properties of these vdWH configurations, our research not only anticipates the emergence of a notable type-III band alignment vdWH but also underscores the potential of 2D vdWHs in optical sensor applications.

Design, optimization, and performance analysis of GaP/Si heterojunction Fin-TFET with MoS2 nanoribbon channel

This article presents the design and optimization of GaP/Si heterojunction Fin-TFET with a MoS2 channel. The elevated fin structure, coupled with ultrathin MoS2 layers and the tuneable bandgap properties of MoS2 material, significantly enhances gate control over the channel and improves device performance. Additionally, the GaP/Si heterojunction with a heavily doped n-type source pocket leads to a narrow barrier junction, promoting Band-to-Band Tunneling (BTBT). The optimized Fin-TFET boasts exceptional electrical characteristics: a high ON-current (7.72 × 10−5 A/μm), an ultra-low OFF-current (4.16 × 10−17 A/μm), and leading to an outstanding ION/IOFF ratio (7.23 × 1012). Furthermore, the device demonstrates a steep subthreshold slope (SS) of 6 mV/dec (point) and 16.8 mV/dec (average), alongside impressive analog performance with a transconductance (gm) of 2.75 × 10−4 S, a cut-off frequency (fc) of 1.3 × 1012 THz, and a gain-bandwidth product (GBP) of 0.17 × 1012 THz. The entire analysis was conducted utilizing the Sentaurus TCAD-3D simulation tool.

Simplified Bilayer TFETS with Oxide And Group-IV Semiconductor For P-Channel Operation

The paper proposes a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV semiconductor (p-IV) heterostructure, allowing for both n- and p-channel TFET operations under the same device structure. The p-IV side in the heterostructure has a metal-oxide-semiconductor (MOS) gate-stack that modulates the surface potential of the p-IV MOS interface and controls the band-to-band tunneling (BTBT) current during p-TFET operation. Technology computer-aided design (TCAD) simulation is used to predict the p-TFET operation with symmetric electrical characteristics to the n-TFET operation. The p-TFET operation of the n-ZnSnO/p-SiGe bilayer device is experimentally demonstrated on a SiGe-on-insulator substrate, under Si back-gate operation. Both n- and p-TFET operations are observed in an identical device by using the top- and back-gate electrodes. Keywords: Bilayer, n-TFET, p-TFET, SiGe, SiGe-on-insulator (SiGeOI), ZnSnO

Investigation of hetero gate oxide hetero stacked triple metal vertical tunnel FET with variable interface trap charges and temperature

The performance of the hetero gate oxide hetero stacked triple metal vertical tunnel FET (HGO-HS-TMG V-TFET) in both dc and analog/RF is examined in this work. GaSb (a low bandgap material) and Si are layered in the source area. The reliability of the device is also examined by analyzing the consequence of interface trap charges (ITC) like donor (positive ITC) and acceptor (negative ITC) at diverse temperature values on DC, analog/RF and linearity performance of the device by dint of Silvaco ATLAS. Simulation shows Shockley-Read-Hall (SRH) phenomena predominate at reduced gate voltage, causing IOFF deterioration that, at high temperatures, results in ION/IOFF degradation. Whereas the band-to-band tunneling (BTBT) phenomenon—which is weakly influenced by temperature changes—is common at high gate voltages. As a result, IOFF degrades at elevated temperatures about a magnitude of 102, going from 10−19 A (200 K) to 10−17 A (400 K). Additionally, at elevated temperature values, it becomes apparent that the cut-off frequency (fT) increases and the threshold voltage (Vth) decreases, which leads to an improvement in device performance. Moreover, ITC alters flat band voltage and gate control, which impacts the device's performance. Device performance is improved when ITC is positive, while it is decreased when ITC is negative.

Challenges and Progress in the Fabrication of Silicon Nanowire Tunnel Diodes

Tunnel (Esaki) diodes prepared in silicon (Si) nanowires could provide a unique platform to investigate band-to-band tunneling (BTBT) transport in nanoscale. However, the successful fabrication of these devices poses substantial challenges, related to controlling high doping concentrations, maintaining the abruptness of the pn junction, and minimizing roughness due to nanoscale patterning. This paper comprehensively addresses these challenges, suggesting potential strategies for optimization. Additionally, examples of nanoscale diodes fabricated so far in silicon-on-insulator (SOI) substrates are showcased, highlighting their tunnel-diode characteristics at low temperatures. Furthermore, the underlying physics is discussed: phonon-assisted tunneling, single-charge tunneling and donor-acceptor compensation. For practical applications, such as photodetectors or tunnel field-effect transistors, room-temperature operation is also required.

A Compact and Ultra-Low-Power Low-Pass Filter Based on Band-to-Band Tunneling Effect

Continuous-time filters with low-frequency cutoff are crucial building blocks in analog signal processing circuits for speech processing and biomedical applications. The design of an integrated continuous-time filter with a cutoff frequency spanning from sub-Hz to a few kHz is constrained by the ultra-low power and area minimization requirement. In this article, we have experimentally demonstrated a low pass filter response using only a single partially depleted (PD) silicon on insulator (SOI) transistor. The proposed novel filter is based on band to band tunnelling (BTBT). This low pass filter is on-chip tunable to provide a wide cutoff frequency ranging from 2 Hz to 20 kHz, with a silicon footprint of 9 μm2 and the maximum power consumption of 0.6 nW in Global Foundries’ (GF) 45 nm RFSOI technology. The proposed tunneling-based filter is less prone to process variations and mismatches as compared to traditional integrated analog filters. The proposed BTBT-based passive RC filter with spurious free dynamic range (SFDR) of 29 dbc, outperforms previously reported filters in the literature in terms of power consumption and area. The ultra-low power consumption and area efficiency make this proposed low pass filter suitable for the multichannel analog front-end low-frequency filters for noise-tolerant neural network-based applications such as speech recognition and electrophysiological signal recognition.

On band-to-band tunneling and field management in NiOx/β-Ga2O3 PN junction and PiN diodes

Due to the non-availability of p-type β-Ga2O3 films, p-type NiO x is gaining attention as a promising alternative to complement the n-type β-Ga2O3 films. This work investigated the band-to-band tunneling (BTBT) related reverse leakage current in NiO x /β-Ga2O3 PN junction diodes. The analysis reveals that a low barrier between the valence band maxima of NiO x and conduction band minima of β-Ga2O3 may promote direct BTBT and trap-assisted BTBT currents during the reverse bias. On the contrary, NiO x /β-Ga2O3 diodes in PiN configuration offer a wider BTBT depletion width and lower peak electric field, lowering the reverse leakage current by orders of magnitude. Thus, we show that NiO x /β-Ga2O3 heterojunction diodes in PiN configuration offer better field management strategies and suppression of the reverse leakage. The analysis performed in this work is thought to be valuable in informing device-design of NiO x /β-Ga2O3 heterojunction diodes for future high-power applications.

Electrical characterization of SOI pMOS device leakage

This work investigates Silicon-on-Insulator (SOI) pMOS leakage current. Temperature measurements indicates the superposition of two leakage mechanisms: band-to-band tunneling (BTBT) and Shockley-Read-Hall Field-Enhanced (SRHFE) generation recombination. Thanks to a dedicated low current measurement setup, the impact of device width (W), thickness (tsi) and polarization (back bias, drain and source) on leakage level is evaluated for both mechanisms.

Modulation of carrier transport in bipolar response BDD/SnO2 p+-n heterojunction UV photodetectors

A unique band-to-band tunneling (BTBT) phenomenon has been discovered in heavily boron-doped diamond (BDD)/SnO2 p+-n heterojunctions. This phenomenon can be modulated by varying the bias voltage, changing the thickness of the SnO2 film, and adjusting the power density of incident UV light. The near-broken-gap band alignment of the BDD/SnO2 heterojunction and the existence of electrons in degenerate states in the valence band of BDD are the key to achieving BTBT. Moreover, BDD/SnO2 p+-n heterojunction UV photodetectors (PDs) prepared by radio-frequency magnetron sputtering exhibit a binary photoresponse, large open-circuit voltage (Voc-l), and high photo/dark current ratio (Ip/Id). Those behaviors can be produced through periodic on/off UV light irradiation and by changing tunneling, drift, and thermionic emission currents. Our work, which is the first to achieve a binary photoresponse by modulating BTBT in BDD/SnO2 heterojunctions, demonstrates the feasibility of extending BTBT theory to logical optoelectronic devices.

Single-Charge Tunneling in Codoped Silicon Nanodevices.

Silicon (Si) nano-electronics is advancing towards the end of the Moore's Law, as gate lengths of just a few nanometers have been already reported in state-of-the-art transistors. In the nanostructures that act as channels in transistors or depletion layers in pn diodes, the role of dopants becomes critical, since the transport properties depend on a small number of dopants and/or on their random distribution. Here, we present the possibility of single-charge tunneling in codoped Si nanodevices formed in silicon-on-insulator films, in which both phosphorus (P) donors and boron (B) acceptors are introduced intentionally. For highly doped pn diodes, we report band-to-band tunneling (BTBT) via energy states in the depletion layer. These energy states can be ascribed to quantum dots (QDs) formed by the random distribution of donors and acceptors in such a depletion layer. For nanoscale silicon-on-insulator field-effect transistors (SOI-FETs) doped heavily with P-donors and also counter-doped with B-acceptors, we report current peaks and Coulomb diamonds. These features are ascribed to single-electron tunneling (SET) via QDs in the codoped nanoscale channels. These reports provide new insights for utilizing codoped silicon nanostructures for fundamental applications, in which the interplay between donors and acceptors can enhance the functionalities of the devices.

A nonvolatile bidirectional reconfigurable FET based on S/D self programmable floating gates.

A nanoscale nonvolatile bidirectional reconfigurable field effect transistor (NBRFET) based on source /drain (S/D) self programmable floating gates is proposed. Comparing to the conventional reconfigurable field effect transistor (RFET) which requires two independently powered gates, the proposed NBRFET requires only one control gate. Beside, S/D floating gates are introduced. Reconfigurable function is realized by programming different types of charges into the S/D floating gates through biasing the gate at a positive or negative high voltage. The effective voltages of the S/D floating gates are determined jointly by the quantity of the charge stored in the S/D floating gates and the gate voltage. In addition, the charge stored in the floating gate has an effect of reducing the energy band bending near the source/drain regions when the gate is reversely biased, thereafter, the band to band tunneling (BTBT) leakage current can be largely decreased. The scale of the proposed NBRFET can be reduced to nanometer level. The device performances such as the transfer and output characteristics are verified by device simulation, which proves that the proposed NBRFET has very good performance in the nanometer scale.