Investigation of hetero gate oxide hetero stacked triple metal vertical tunnel FET with variable interface trap charges and temperature

Abstract

The performance of the hetero gate oxide hetero stacked triple metal vertical tunnel FET (HGO-HS-TMG V-TFET) in both dc and analog/RF is examined in this work. GaSb (a low bandgap material) and Si are layered in the source area. The reliability of the device is also examined by analyzing the consequence of interface trap charges (ITC) like donor (positive ITC) and acceptor (negative ITC) at diverse temperature values on DC, analog/RF and linearity performance of the device by dint of Silvaco ATLAS. Simulation shows Shockley-Read-Hall (SRH) phenomena predominate at reduced gate voltage, causing IOFF deterioration that, at high temperatures, results in ION/IOFF degradation. Whereas the band-to-band tunneling (BTBT) phenomenon—which is weakly influenced by temperature changes—is common at high gate voltages. As a result, IOFF degrades at elevated temperatures about a magnitude of 102, going from 10−19 A (200 K) to 10−17 A (400 K). Additionally, at elevated temperature values, it becomes apparent that the cut-off frequency (fT) increases and the threshold voltage (Vth) decreases, which leads to an improvement in device performance. Moreover, ITC alters flat band voltage and gate control, which impacts the device's performance. Device performance is improved when ITC is positive, while it is decreased when ITC is negative.