Band Edge Work Function Research Articles

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS1st/NMOS1st Laminated Stack for PMOS Low Power Target

In this paper, the band-edge work function performance is systematically investigated and modulated via novel nitrogen plasma treatment (NPT) with the advanced PMOS1st (TiN/TiN/TiAlC) and NMOS1st (TiN/TiN) laminated stacks for the fabricated PMOS capacitors. The basic multi-VT performance is strongly modulated by controlling NPT process. 1) Flatband voltage (VFB) shifts towards band edge are obtained as +120 mV (undiluted), +430 mV (diluted) for PMOS1st and +80 mV (undiluted), +210 mV (diluted) for NMOS1st. 2) By manipulating the NPT process from undiluted and diluted case, it can provide significant high band-edge effective work function ranging from 4.89 eV (undiluted) to 5.21 eV (diluted) for PMOS1st and 5.22 eV (undiluted) to 5.35 eV (diluted) for NMOS1st laminated stack, respectively. 3) NPT diluted with hydrogen is observed to maintain ultralow bulk trap density (1.11 × 1011 cm−2 for PMOS1st and nearly zero for NMOS1st) and interface trap density (3.34 × 1011 eV−1 cm−2 for PMOS1st and 6.45 × 1011 eV−1 cm−2 for NMOS1st). The significant band-edge work function modulation and very low bulk and interface trap density demonstrate the novel NPT with PMOS1st/NMOS1st laminated stack is very promising to achieve the target of PMOS low-power application in the further technology node.

Band-Edge Work Function Obtained by Plasma Doping TiN Metal Gate for nMOS Device Application

This paper proposed, for the first time, that the band-edge effective work functions (EWFs) are achieved by employing PH3 plasma doping (PLAD) TiN metal gate for nMOS device application under replacement metal gate and high dielectric constant (k) dielectric/metal gate last nMOS device. The effects of PLAD energy, dose, gas mixture, and postdoping cleaning procedure on the EWF, EOT, and properties of TiN/HfO2/ILSiO2 gate-stack are investigated; the corresponding possible mechanisms are discussed. Suitable low threshold voltages of nMOSFETs are obtained, while shrinking the EOT. It reduces the corner effect on trench gate doping uniformity, which is induced by shadowing effect in the beam-line implantation technology, to a minimum. It has the potential for the further aggressively scaled 3-D CMOS device and beyond application.

Fundamental Limits on the Subthreshold Slope in Schottky Source/Drain Black Phosphorus Field-Effect Transistors.

The effect of thickness, temperature, and source-drain bias voltage, V(DS), on the subthreshold slope, SS, and off-state properties of black phosphorus (BP) field-effect transistors is reported. Locally back-gated p-MOSFETs with thin HfO2 gate dielectrics were analyzed using exfoliated BP layers ranging in thickness from ∼4 to 14 nm. SS was found to degrade with increasing V(DS) and to a greater extent in thicker flakes. In one of the thinnest devices, SS values as low as 126 mV/decade were achieved at V(DS) = -0.1 V, and the devices displayed record performance at V(DS) = -1.0 V with SS = 161 mV/decade and on-to-off current ratio of 2.84 × 10(3) within a 1 V gate bias window. A one-dimensional transport model has been utilized to extract the band gap, interface state density, and the work function of the metal contacts. The model shows that SS degradation in BP MOSFETs occurs due to the ambipolar turn on of the carriers injected at the drain before the onset of purely thermionic-limited transport at the source. The model is further utilized to provide design guidelines for achieving ideal SS and meet off-state leakage targets, and it is found that band edge work functions and thin flakes are required for ideal operation at high V(DS). This work represents a comprehensive analysis of the fundamental performance limitations of Schottky-contacted BP MOSFETs under realistic operating conditions.

Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high-k (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ion-implanted TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /ILSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /ILSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

Integration of Advanced MOSFET Device with Dual Effective Band Edge Work Function Metals Using Both HK and MG Last Scheme

The aggressive downscaling of CMOS requires both lateral and vertical shrinkage of dimensions. SiO2 served as gate dielectrics for more than four decades now is with severe leakage problem with quantum mechanical tunneling effect due to SiO2has been scaled down to only a few atomic layers to boost device performance. Thus high dielectric constant materials such as Hafnium oxide and Hafnium silicate are of great interests in recent years [1]-[3]. Meanwhile HK layers are not perfectly compatible with silicon channel surface as traditional silicon dioxide due to interface trap, dipole and defect are formed during processing which would be difficult for threshold voltage tuning. Gate stacks engineering like interfacial layer, post dielectric anneal and metal gate are needed to be carefully handled to alleviate these side effects. Due to excellent EOT scaling and short channel effect controllability, HKMG has been implemented into modern bulk silicon device to replace traditional Poly/SiON process. Different from Poly/SiON process which poly gate can be doped with N type and P type dopants respectively for NFET and PFET threshold voltage adjustment, Metal gate last process integration needs two kinds of metal to tune MOSFET work function in order to achieve suitable device performance [4, 5]. In this work, we have successfully fabricated devices with dual effective work function metals with 4.15eV and 5.04eV for NFET and PFET respectively. With EWF close to band edge, threshold voltage can be effectively achieved with 0.35V and -0.31V for NFET and PFET respectively. Process conditions and electrical results are also discussed.TiN served as PMOS work function metal and TiAl chosen as NMOS work function metal are integrated into CMOS. The detail integration flow of HKMG and TEM of cross section of gate structure are shown in Figure.1.In Fig. 2, threshold voltages with different Al% concentration are plotted. It can be shown that threshold voltage is strongly dependent on Al atomic concentration. With more percentage of concentration of Al, Vt would be lower due to work function Fermi level close to conduction band edge. Table.1 shows the effective work function values for NFET and PFET respectively. The EWFs are both close to band edges which are suitable for Vt tuning for devices. Fig.3 shows the NFET and PFET Id-Vg curves with low DIBL and sub-threshold swing performance. DIBL can be as low as 78mV/V and 82mV/V for NFET and PFET respectively. Swing can be as low as 62mV/dec and 64mV/dec for NFET and PFET respectively. It effectively demonstrates that controllability for metal gate to channel is much better comparing with Poly/SiON gate stackIn conclusion, we have successfully fabricated NFET and PFET devices with both HK and MG last integration scheme. By optimizing process conditions, Both NFET and PFET effective work functions can be tuned to be close to band edges with TiAl as NFET work function metal and TiN as PFET work function metal. Al concentration impaction on Vt is analyzed. Vt are well controlled with different channel length. DIBL and Swing are as low as to 78mV/V and 82mV/V and 62mV/dec and 64mV/dec for NFET and PFET respectively.

Integration of Advanced MOSFET Device with Dual Effective Band Edge Work Function Metals Using Both HK and MG Last Scheme

A 22nm MOSFET device was presented with bulk Si planar process integration in this paper. We have achieved NFET and PFET drive current of 539μA/μm and 801μA /μm respectively with novel high k and metal gate stack. Excellent DIBL and Swing performance were achieved with 78mV/V and 82mV/V and 62mV/dec and 64mV/dec for NFET and PFET respectively. TiAl alloy with optimized Al concentration and process power as NFET work function metal and TiN with optimized process power, bias and concentration as PFET work function metal were chosen in our experiments. Effective work functions for both NFET and PFET were adjusted to band edge with 4.15eV and 5.04eV respectively by process optimization.

(Invited) Conformal Metal Gate Process Technology for 14nm Logic Node and Below

Emerging 3D transistor structures and continued scaling requires conformal metal gate options with low resistivity, band edge work function and improved barrier properties. Doping ALD TiN with Si improves barrier properties shown with 10X reduced gate leakage. Both valence and conduction band edge work function can be met with low resistivity conformal films. The combination of ALD TiN, CVD Co and CVD Al can be used for low resistivity replacement metal gate fill for sub-15nm trenches.

Effect of oxygen on tuning the TiNx metal gate work function on LaLuO3

This paper presents experimental evidence on effective work function tuning due to the presence of oxygen at the TiNx/LaLuO3 interface. Two complementary techniques, internal photoemission and X-ray photoelectron spectroscopy, show good agreement on the position of the metal gate Fermi level to conduction (2.79±0.25eV) and valence (2.65±0.08eV) band edge for TiNx/bulk LaLuO3 gate stacks. The chemical shifts of Ti2p and N1s core levels and different degree in ionicity of TiNx metal gates correlate with the observed valence band offset shifts. The results have significance for setting the band edge work function and resulting low threshold voltage for ultimately scaled LaLuO3-based p-metal oxide semiconductor field effect transistor devices.

Gallium-Incorporated TiN Metal Gate With Band-Edge Work Function and Excellent Thermal Stability for PMOS Device Applications

A cost-effective method for modulating the effective work function (EWF) of a metal gate while simultaneously decreasing the equivalent oxide thickness (EOT) of a high-k dielectric is proposed for the first time. By incorporating gallium (Ga) into the TiN/HfLaON/interfacial layer (IL) SiO2 PMOS gate stack, a band-edge EWF of 5.18 eV and an EOT of 0.57 nm can be obtained. Excellent thermal stability was maintained even after the post metal anneal (PMA) at 1000°C. The impacts of TiN thickness, Ga implant doses, and PMA conditions on the properties of the Ga-incorporated TiN/HLaON/IL SiO2 gate stack are investigated, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the gate-first process flow to fabricate PMOSFETs with a minimum gate length of 28 nm.

Optimizing Band-Edge High-κ/Metal Gate n-MOSFETs with ALD Lanthanum Oxide Cap Layers: Oxidant and Positioning Effects

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.

Metal Carbides for Band-Edge Work Function Metal Gate CMOS Devices

Various metal carbides (TaC, HfC, WC, and VC) were thoroughly investigated for metal gate CMOS devices with band-edge work functions (WFs). It is found that TaC and HfC are more suitable for the CMOS device application among the various metal carbides. HfC is demonstrated to be a good candidate for NMOS because of its low WF and excellent thermal stability, while TaC Al shows a high WF and good thermal stability suitable for PMOS device application. In addition, HfC and TaC have a wide range of WF tunability using thin LaN and AlN interlayer or introduction of La and Al into the metal carbides.

CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

Oxygen vacancies in high-k oxides

High dielectric constant (K) gate oxides such as HfO 2 have suffered from charge trapping, threshold voltage shifts and a difficulty of metal or poly-Si gates to achieve band edge work function values. We investigate how these are related to the oxygen vacancies in a series of ab-initio calculations. The O vacancy is found to correlate with optical, luminescence and charge pumping spectra. The O vacancy contributes to the Fermi level pinning effect, which limits the band edge work functions. Inhibiting motion of vacancies may allow less pinning of gate electrode work functions.

Band-edge metal gate materials for atomic-layer-deposited HfO 2 for future CMOS technology

In this paper, two different materials are studied for silicon band edge work function. Sc metal gate with thin interface TaN x layer is investigated for n-channel metal-oxide semiconductor (NMOS) metal gate application. The control of TaN x layer thickness is necessary to achieve improved thermal stability and work function (WF) as low as 4.0 electron volts (eV). RuO x also has been demonstrated for p-channel metal-oxide semiconductor (PMOS) application. RuO x WF tends to increase in comparison with elemental Ru metal. This may be due to improved thin film properties like better adhesion and roughness for RuO x . Overall both Sc and RuO x are revealed as candidate materials for future CMOS technology.

Feasibility of Dipole Based Work Function Tuning for Sub-1nm EOT Metal Gated High-K Stacks

Band edge work functions and hence low VTS are still a difficult challenge for most metal gated high-K dielectric stacks due to uncontrolled reaction layers which result in dipoles and impact the band bending in the substrate. One example of this unwanted dipole formation is the reported oxygen vacancy at the metal-HfO2 interface which acts to reduce the effective work function of PMOS metals [1]. Furthermore, the composition and thicknesses of all layers in the gatestack and the process history also influence the final value of the effective work function.

A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS

The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.