Abstract
A cost-effective method for modulating the effective work function (EWF) of a metal gate while simultaneously decreasing the equivalent oxide thickness (EOT) of a high-k dielectric is proposed for the first time. By incorporating gallium (Ga) into the TiN/HfLaON/interfacial layer (IL) SiO2 PMOS gate stack, a band-edge EWF of 5.18 eV and an EOT of 0.57 nm can be obtained. Excellent thermal stability was maintained even after the post metal anneal (PMA) at 1000°C. The impacts of TiN thickness, Ga implant doses, and PMA conditions on the properties of the Ga-incorporated TiN/HLaON/IL SiO2 gate stack are investigated, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the gate-first process flow to fabricate PMOSFETs with a minimum gate length of 28 nm.
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