Backside Of Substrate Research Articles

High inter-element isolation and WLAN filtering mechanism: A compact MIMO antenna scheme

A multiple-input-multiple-output (MIMO) wireless local area network (WLAN) band-notched antenna with high inter-element isolation is proposed. The proposed MIMO system is composed of two monopole antennas, each composed of a slotted radiating patch and a stepped ground plane. The embedded slots and the ground plane steps are wisely located to achieve the desired wide band functionality as well as WLAN band-notched realization. The overall size of the MIMO antenna is 20 × 34 mm2 printed on 1.6 mm FR4 substrate. Moreover, to reduce the coupling between the constituent monopole antennas and enhance the isolation, a parasitic element is embedded between the antennas on the substrate backside. By wise tuning of the position and dimensions of the parasitic element, high isolation is achieved which is necessary for MIMO communication systems. Both simulation and measured results confirm a 10-dB impedance bandwidth of 2.6–11.2 GHz excluding the rejected band for |S11| ≤ −10 dB, and |S21| ≤ −20 dB. Wide bandwidth, small size, and band-notched feature are some of the merits of the proposed MIMO antenna. Detailed analysis on the antenna performance are released in detail throughout the paper.

(Invited) Recent Advances in SiC CMP

The need for high-quality single crystal SiC substrates continues to grow as the demand for SiC-based power and RF devices increases. The physical properties of SiC result in better thermal conductivity, higher breakdown voltage, faster switching performance and lower resistivity when compared to similar devices based on silicon. Even with the performance advantages, the adoption rate of SiC is slowed by high cost and inherent difficulty of processing the material. Conventional processing of SiC substrates involves double-sided batch lapping followed by batch diamond polishing then final polishing with a non-diamond slurry to achieve an epi-ready surface. This process flow involves multiple process tools and is fraught with issues including the need for wafer sorting to group wafers by thickness, manual loading and unloading of wafers, low yields, and unacceptable risk of batch loss (an entire batch of wafers may be scrapped if even one wafer cracks or breaks during process). This paper presents an improved process for single-wafer CMP during SiC substrate manufacturing or backside thinning. In contrast to batch polishing, key improvements include individual wafer processing, fully-automated handling, and elimination of the need for wafer sorting and grouping by thickness. Recent development efforts have achieved removal rates for the 4H Si face up to 2.5 µm/hour for the first step CMP. Removal rates for the C-face can be as much as 3-4x higher consistent with other findings in the industry. Fig 1 shows surface finish after the polishing sequence is complete which is consistently at or below 1 Å Ra as measured by AFM. The combination of an optimized grind followed by an optimized CMP process provides a viable path to both improving wafer yield and reducing costs for SiC wafer manufacturing or backside thinning process sequences. Figure 1

Circular polarization realization in array antennas by a modified sequential phase feeding mechanism of linearly polarized elements

AbstractNovel designs of a circularly polarized 2 × 2 and 4 × 4 slot array antennas (CPSAAs) are proposed. Sequential phase feed network composed of a section of 270° and four strips is utilized to feed the array structures. Array elements are simple linearly polarized wide slot antennas (WSAs) composed of simple radiating patches with truncation on four corners and slotted ground plane on substrate backside. Each WSA operates over the UWB frequency band of 3.1–10.6 GHz. When the WSAs are arranged in the form of 2 × 2 and 4 × 4 CPSAAs, frequency bands of 3–13.1 and 1.4–12.3 GHz are covered, respectively. More importantly, CP is generated at 4.5–8 and 4.6–8.8 GHz for 2 × 2 and 4 × 4 CPSAAs, respectively. This is while; the WSAs are linearly polarized elements. Higher gain values and wider bandwidths are obtained with respect to single WSA. Design process and performance analysis of the single and array antennas are discussed through the paper.

Compensating film stress in thin silicon substrates using ion implantation.

Future space telescopes, especially X-ray telescopes, will require thin mirrors to achieve high optical throughput. Thin mirrors are more difficult to fabricate than thick mirrors, but recent advances have made accurate fabrication of thin mirrors possible. However, mirrors must have a reflective coating, which typically has non-repeatable and non-uniform intrinsic stress that deforms a thin mirror. Reducing coating stress by controlling deposition parameters typically reduces reflectivity. Non-uniform integrated stress compensation (NISC) methods, in which spatially controlled stress is applied to the mirror substrate backside to balance the frontside coating stress, decouple the film stress from the reflectivity. Ion implantation is one NISC method, where high-energy ions are implanted into a glass or silicon substrate to generate stress near the substrate surface. In this paper, we demonstrate the use of ion implantation for stress compensation of 30 nm thick chromium films applied to the front of five silicon wafers. The reflective films have mean integrated stress between -8 and -35 N/m, which cause deformations between 400 and 1600 nm RMS. We demonstrate that these wafers can be restored to the pre-coating shape to within 60 nm RMS, in most cases within 1/20th of the coating deformation.

Investigation of the Impact of External Stress on Memory Characteristics by Modifying the Backside of Substrate

The effects of the external stress on memory device characteristics are numerically discussed, and experimental observations are made, based on the wafer curvature method for extraction of stress. An analysis of the interface state is then performed. The external force applied to the device was controlled by depositing a metal film on the wafer backside; then, the residual stress induced on the substrate was extracted. We observed that the dangling bond generated by the residual stress increases the trap site and deteriorates the interface properties. A resulting degradation of cell characteristics occurred, including an increase in the leakage current and degradation of the memory window, featuring a reduction in the oxide/nitride/oxide trap density, which worsens as the magnitude of stress increases. From these results, we concluded that minimizing the stress is essential for retaining the cell characteristics. Especially, our results are expected to be of great help in determining the effect of external force on the memory characteristics during the back-end-of-line processing.

GaN-Based Ultraviolet Passive Pixel Sensor on Silicon (111) Substrate.

The fabrication of a single pixel sensor, which is a fundamental element device for the fabrication of an array-type pixel sensor, requires an integration technique of a photodetector and transistor on a wafer. In conventional GaN-based ultraviolet (UV) imaging devices, a hybrid-type integration process is typically utilized, which involves a backside substrate etching and a wafer-to-wafer bonding process. In this work, we developed a GaN-based UV passive pixel sensor (PPS) by integrating a GaN metal-semiconductor-metal (MSM) UV photodetector and a Schottky-barrier (SB) metal-oxide-semiconductor field-effect transistor (MOSFET) on an epitaxially grown GaN layer on silicon substrate. An MSM-type UV sensor had a low dark current density of 3.3 × 10−7 A/cm2 and a high UV/visible rejection ratio of 103. The GaN SB-MOSFET showed a normally-off operation and exhibited a maximum drain current of 0.5 mA/mm and a maximum transconductance of 30 μS/mm with a threshold voltage of 4.5 V. The UV PPS showed good UV response and a high dark-to-photo contrast ratio of 103 under irradiation of 365-nm UV. This integration technique will provide one possible way for a monolithic integration of the GaN-based optoelectronic devices.

Simulation of Tandem Thin-Film Solar Cell on the Basis of CuInSe2

CuInSe2 thin-film solar cells are promising materials for photovoltaic devices. One of the main tasks of researchers is to find ways to increase the solar cells efficiency. In this paper we propose an original structure of a thin-film solar cell based on a tandem connection of a photoelectric converter and a thermoelectric layer based on CuInSe2. The photoelectric converter consists of CuInSe2 and CdS layers. A 3D model of the proposed thin-film solar cell was implemented in the COMSOL Multiphysics environment with using the Heat Transfer module. The simulation was carried out taking into account the diurnal and seasonal variations of both the ambient temperature and the power density of the AM1.5 solar spectrum for the geographical coordinates of Minsk. The solar radiation power density of about 500 kW/m2 can be achieved by using concentrators. The temperature pattern and temperature gradients are calculated in each layer of the solar cell without and with the temperature stabilization of the substrate back side as well as without and with the thermal insulation of the substrate ends. Graphs of the temperature gradients of the thermoelectric layer and the temperature variations of the photoelectric converter of the solar cell are given. As a result of the simulation, it is shown how the uneven heating of both the surface of a thin-film solar cell and its layers occur under conditions of diurnal and seasonal variations of both the ambient temperature and the solar radiation power density. Under concentrated solar radiation exposure, the photoelectric converter surface can be heated up to 700 °C without temperature stabilization of the solar cell substrate. The operating temperature of the photoelectric converter was maintained at no more than 2.35 °C in January and at no more than 14.23 °C in July due to the temperature stabilization of the substrate back side of the proposed device. This made it possible to achieve an increase in the output power of the solar cell both by summing the photoand thermoelectric output voltages and by the concentration of solar radiation.

Fabrication of dual-termination Schottky barrier diode by using oxygen-/fluorine-terminated diamond

Fabrication of dual-termination Schottky barrier diode (SBDDT) by using oxygen-/fluorine-terminated diamond (OT-/FT-diamond) has been carried out on P-/P+ diamond. X-ray photoelectron spectroscopy (XPS) measurement was used to determine the chemical composition of OT-/FT-diamond surface treated by ultraviolet ozone and C4F8 plasma, respectively. The barrier heights of Au on OT-/FT-diamond were calculated to be 2.0 ± 0.12 and 2.39 ± 0.12 eV, respectively. Au film was patterned on the OT-/FT-diamond as the schottky electrode, and Ti/Au film were deposited on the backside of substrate as ohmic electrode, then a SBDDT was achieved completely. SBDDT exhibits better forward and reverse I-V characteristics based on the optimum OT-/FT-diamond (WO/WF) area ratio 0.2, which illustrates that the combination of dual surface termination is an efficient way to optimize the performance of diamond SBD.

Solution processed flexible organic thin film back-gated transistors based on polyimide dielectric films

An organic thin film back-gated transistor (OBGT) was fabricated and characterized. The gate electrode was printed on the back side of substrate, and the dielectric layer was omitted by substituting the dielectric layer with the polyimide (PI) film substrate. Roll-to-roll (R2R) gravure printing, doctor blading, and drop casting methods were used to fabricate the OBGT. The printed OBGT device shows better performance compared with an OTFT device based on dielectric layer of BaTiO3. Additionally, a calendering process enhanced the performance by a factor of 3 to 7 (mobility: 0.016 cm2/V·s, on/off ratio: 9.17×103). A bending test was conducted to confirm the flexibility and durability of the OBGT device. The results show the fabricated device endures 20000-cyclic motions. The realized OBGT device was successfully fabricated and working, which is meaningful for production engineering from the viewpoint of process development.

Stereo analysis on the keyhole and weld pool behaviors in K-PAW with triple CCD cameras

A synchronous visual sensing system was established to observe the topside weld pool, keyhole entrance and keyhole exit at the same time during keyhole plasma arc welding (K-PAW). Complete topside weld pool was captured by a common CCD camera perpendicularly to the welding direction. Meanwhile another two cameras were employed to monitor the keyhole entrance from the rear view and to capture the keyhole exit from the substrate backside, respectively. The evolution process of the weld pool and keyhole behaviors and shapes along with the heat input accumulation were observed. The mechanism of the interactions were discussed and analyzed. Image registration was conducted fusing the weld pool, keyhole entrance and keyhole exit in the same coordinate system. The geometrical dimensions were measured and could reflect the interior intense interactions. Comprehensive investigation of the complicated physical process provided some fundamental and profound understandings.

Slow-wave coplanar waveguides based on inductive and capacitive loading and application to compact and harmonic suppressed power splitters

In this paper, a slow-wave transmission line implemented in coplanar waveguide technology, based on simultaneous inductive and capacitive loading, is presented for the first time. The shunt capacitors are achieved by periodically etching transverse strips in the back substrate side, connected to the central strip through metallic vias. The series inductors are implemented by etching rectangular slots in the ground plane. The effect of these reactive elements is an enhancement of the effective shunt capacitance and series inductance of the line, leading to a significant reduction of the phase velocity (slow-wave effect). Consequently, the guided wavelength is also reduced, and these lines can be applied to the miniaturization of microwave components. Moreover, due to periodicity, these artificial lines exhibit stop bands (Bragg effect) useful for spurious or harmonic suppression. A compact harmonic suppressed power splitter, based on a slow wave 35.35 Ω impedance inverter, has been designed and fabricated in order to demonstrate the potential of the proposed approach. The length of the inverter is 48% the length of the conventional counterpart, and measured power splitting at the first (3f0) and second (5f0) harmonic frequencies is rejected more than 49 and 23 dB, respectively.

Application of Split Ring Resonator (SRR) Loaded Transmission Lines to the Design of Angular Displacement and Velocity Sensors for Space Applications

The accurate measurement of the angular displacement and velocity of reaction wheels is necessary for attitude (orientation) control in space vehicles (satellites). In this paper, microwave, contactless, and low-cost (as compared to optical encoders) sensors useful for that purpose are analyzed in detail. The sensor consists of a rotor and a stator. The rotor is a disk (or a circular crown) of dielectric material, where one or several arrays of equidistant single-loop split ring resonators (SRRs) are etched along its edge, forming circular chains of hundreds of SRRs. The stator is a coplanar waveguide (CPW) also loaded with pairs of single-loop SRRs (etched in the back substrate side), with the centers located in the slot region. The sensing principle is based on the amplitude modulation of a harmonic (single-tone continuous wave) feeding signal, achieved when the chains of the rotor are displaced over the SRR pairs of the stator. Both sensor elements (rotor and stator) must be parallel oriented, with the SRR pairs of the CPW in close proximity to the SRR chains of the rotor (and rotated 180°), in order to favor their coupling. By this means, the transmission coefficient of the CPW is varied by the circular motion of the rotor, and significant amplitude modulation of the feeding signal is achieved. From the envelope function, the angular velocity can be accurately determined. With the proposed sensors, instantaneous and practically unlimited rotation speeds can be measured.

Fabrication of Deep 4H-SiC Microstructures Via Inductively Coupled SF6/O2 Plasma

High aspect ratio deep reactive ion etching (DRIE) of single-crystalline silicon carbide (SiC) holds promise for fabricating next-generation harsh-environment (e.g. high temperature, high power, reactive environments) micro- and nanoelectromechanical systems (MEMS/NEMS). However, unlike Si, SiC microfabrication via DRIE remains in its infancy. In particular, high aspect ratio SiC DRIE poses a significant challenge in SiC MEMS development. To tackle this issue, SiC DRIE process parameters (e.g. cycle time, power, backside substrate cooling) were investigated to achieve high aspect ratio SiC microstructures with close to vertical sidewalls. Overall, the SiC processing work described here helps to bridge the knowledge gap between Si and SiC microfabrication and support the adaption of single-crystalline SiC-based micro- and nanodevices.

Patterned films by atomic layer deposition using Parafilm as a mask

This paper presents a new method for depositing patterned films by atomic layer deposition (ALD) using Parafilm as a mask to block the film growth on selected areas of the substrate surface. This offers an easy and efficient method for large area patterning from the millimeter to even meter scale as needed, for example, for protecting contact areas in integrated circuits and microelectromechanical system devices and in preventing film growth on the backside of substrates. It is shown here that Parafilm can protect the substrate against Al2O3, TiO2, and Ir film growth effectively. However, outgassing from the Parafilm affects the film growth on the unmasked areas differently for the three materials. For Al2O3, there are no significant effects on the growth rate and film quality on the nonmasked areas and the thickness profiles next to the Parafilm masked areas are narrow. For TiO2 and Ir, by contrast, the thickness profiles are wider and outgassing also slows down the Ir growth. Energy dispersive x-ray analysis confirms that Ir does not grow on Parafilm. Al2O3 and TiO2 films do grow on Parafilm, but after the ALD process, the Parafilm can be peeled off easily with tweezers and the areas under the Parafilm mask are without any deposition.

Deep reactive ion etching of 4H-SiC via cyclic SF6/O2 segments

Cycles of inductively coupled SF6/O2 plasma with low (9%) and high (90%) oxygen content etch segments are used to produce up to 46.6 µm-deep trenches with 5.5 µm-wide openings in single-crystalline 4H-SiC substrates. The low oxygen content segment serves to etch deep in SiC whereas the high oxygen content segment serves to etch SiC at a slower rate, targeting carbon-rich residues on the surface as the combination of carbon-rich and fluorinated residues impact sidewall profile. The cycles work in concert to etch past 30 µm at an etch rate of ~0.26 µm min−1 near room temperature, while maintaining close to vertical sidewalls, high aspect ratio, and high mask selectivity. In addition, power ramps during the low oxygen content segment is used to produce a 1:1 ratio of mask opening to trench bottom width. The effect of process parameters such as cycle time and backside substrate cooling on etch depth and micromasking of the electroplated nickel etch mask are investigated.

Light extraction enhancement of AlGaN-based ultraviolet light-emitting diodes by substrate sidewall roughening

The effect of sapphire substrate's sidewall roughening on light extraction of AlGaN-based ultraviolet light-emitting diodes (UV LEDs) is investigated. Finite-difference time-domain simulation reveals that a roughening region for effective light extraction enhancement exists on the substrate's sidewall. Roughening outside the effective roughening region will result in undesirable inward photon scattering and absorption. For TM-polarization-dominated deep-UV LEDs, the effective roughening region is from the substrate's backside to the position about L/2 × tan(θc) away from the substrate's front side, where L is the side length of the LED device and θc is the critical angle of total reflection. In the LED device fabrication, picosecond laser dicing is employed to realize roughening layers on the sapphire substrate's sidewalls. The UV LEDs with three roughening layers have 13.2% higher average light output power (LOP) at 20 mA than those with two roughening layers, thanks to the larger roughening area in the effective roughening region. When additional roughening layers beyond the effective roughening region are applied, the LOP decreases as the simulation predicts. Furthermore, the values of leakage current and forward voltage of these LEDs are consistently below 0.2 μA at −10 V and 5.8–6.0 V at 20 mA, respectively, showing no thermal damage to intrinsic diode performance by the laser processing.

A Novel Photodetector Based on Azo/SiO x /N-Si Heterojunction Structure

Recently, photodetector based on semiconductor-insulator-semiconductor (SIS) heterojunction structure which contains indium zinc oxide (IZO) as the transparent conductive oxide (TCO) layer was reported. In that work, IZO layer was deposited by pulsed laser deposition which is impractical to the large-area device production. Moreover, the IZO contains indium which becomes a scarce element due to the vast demand in solar cell and display industries in recent years. In order to overcome these difficulties, aluminum zinc oxide (AZO) was adopted to replace IZO as the TCO layer and the feasibility of AZO/SiO x /n-Si SIS structure to photodetection was investigated. The SIS structure was prepared firstly by growing SiO x layer with appropriate thickness (~1.8 nm) on n-type Si wafer substrate by dry thermal oxidation method. Radio-frequency sputtering was then adopted to deposit a 200-nm thick AZO layer on SiO x /Si substrate. Afterward, the 100-nm thick aluminum layers were deposited by e-beam evaporation to form the bottom electrodes on the backside of Si substrates and the top finger electrodes on AZO layer, respectively, to complete the SIS photodetector preparation. Without applying external bias, the sample with quick photo-response time less than 10 msec and photoresponse (R) of 0.17, 0.67 and 0.22 AW-1separately under the 365-nm, 650-nm and 940-nm illuminations were achieved. The lower R value at short-wavelength illumination was attributed to the absorption of AZO layer since the photon energy of incident light is close to the absorption edge of AZO. The sample was further annealed at 300°C for 1 hr in air ambient and the improvement of R values, 0.27, 1.60 and 0.67 AW-1 under the 365-nm, 650-nm and 940-nm illuminations, was observed. The improvement of R values of the device was ascribed to the reduction of interface trap density (Dit ) at the AZO/SiO x and SiO x /n-Si interfaces as revealed by the capacitance-voltage measurement. The annealing treatment reduced the Dit from 1.63×1012 to 2.80×1011 eV-1cm-2, which efficiently alleviated the carrier capture at interfaces and improved the photodetection properties of the sample. Keywords : Photodetector; Aluminum zinc oxide; Semiconductor-insulator-semiconductor heterojunction; interface trap density.

Simultaneous enhancement of light absorption and improved charge collection in PTB7-Th: PC70BM organic solar cells

ABSTRACTEnhancing the light absorption and improving the charge collection are considered as two major prerequisite for achieving highly efficient bulk heterojunction organic solar cells (BHJ OSCs). In the present study, we have explored Ga doped ZnO as an electron transport layer for improving the charge collection in one of the promising donor: acceptor system comprised of Poly[4,8-bis(5-(2-ethylhexyl)thiophen-2-yl)benzo[1,2-b;4,5-b’]dithiophene-2,6-diyl-alt-(4-(2-ethylhexyl)-3-fluorothieno[3,4-b]thiophene-)-2-carboxylate-2-6-diyl)] (PTB7-Th):phenyl-C71-butyric acid methyl ester (PC70BM). With the inverted geometry having a configuration of ITO/GZO (40nm)/PTB7-Th: PC70BM (100nm)/MoO3 (10nm)/Ag (100nm), maximum power conversion efficiency (PCE) of 7.24% has been achieved, while it is limited at 6.89% for devices with undoped ZnO.It was found that PCE can be further improved to 8.35 % after V-grooved textured PDMS films were attached to the backside of OSC substrates. We attribute this performance enhancement in OSCs is due to increased total optical path length of the incident light within the device.

Insights on the High-Temperature Operational Limits of ZrO2-Y2O3 TBCs Manufactured via Air Plasma Spray

The effective high-temperature operation limit of a ZrO2-7-8 wt.%Y2O3 (YSZ) thermal barrier coating (TBC) manufactured via air plasma spray (APS) is considered to be ~1300 °C. This is related to the metastable tetragonal t′-phase formed during the rapid quenching of the YSZ particles during spraying. The t′-phase transforms into the equilibrium tetragonal and cubic phases at temperatures ≥~1300 °C, which can lead to the formation of the monoclinic phase of YSZ upon cooling to room temperature. This formation of the monoclinic phase is accompanied by a volume expansion that leads to TBC failure due to extensive micro-cracking. To further investigate this limitation, an APS YSZ TBC was sprayed on a CMSX-4 substrate. By using a thermal (laser) gradient cyclic testing, a temperature gradient was generated across the TBC/substrate system. The YSZ T-front and substrate backside T-back temperature levels were ~1500 and ~1000 °C, respectively. In cycle conditions (5-min or 1-h hot and 2-min cool), no TBC failure has been observed. This behavior was partially attributed to the unexpected absence of the monoclinic phase of the YSZ in the cycled coatings. Although preliminary, these results are promising regarding increasing the effective high-temperature operational limits of APS YSZ TBCs.

Efficient light trapping and interface engineering for performance enhancement in PTB7-Th: PC70BM organic solar cells

Inefficient light absorption and poor charge separation are considered as two major bottlenecks for achieving highly efficient bulk heterojunction organic solar cells (BHJ OSCs). In the present study, we have introduced an additional phenyl-C71-butyric acid methyl ester (PC70BM) layer to modify the interface between ZnO based electron transport layer (ETL) and photoactive layer comprised of Poly[4,8-bis(5-(2-ethylhexyl)thiophen-2-yl)benzo[1,2-b; 4,5-b′]dithiophene-2,6-diyl-alt-(4-(2-ethylhexyl)-3-fluorothieno[3,4-b]thio-phene-)-2-carb-oxylate-2-6-diyl)] (PTB7-Th):PC70BM. This interface engineering has quenched the electron–hole recombination at the interface and has improved power conversion efficiency (PCE) from 6.65 to 7.74%. Devices were fabricated in an inverted geometry having a structure ITO/ZnO (40 nm)/PC70BM (5 nm)/PTB7-Th:PC70BM (70 nm)/MoO3 (10 nm)/Ag (100 nm). Additionally, V-grooved textured PDMS films were attached to the backside of OSC substrates which has further improved PCE to 9.12%. Our study suggests that the performance enhancement as observed in OSCs with V-grooved textured PDMS films could be due to increased total optical path length of the incident light within the device.