(Invited) Recent Advances in SiC CMP

Abstract

The need for high-quality single crystal SiC substrates continues to grow as the demand for SiC-based power and RF devices increases. The physical properties of SiC result in better thermal conductivity, higher breakdown voltage, faster switching performance and lower resistivity when compared to similar devices based on silicon. Even with the performance advantages, the adoption rate of SiC is slowed by high cost and inherent difficulty of processing the material. Conventional processing of SiC substrates involves double-sided batch lapping followed by batch diamond polishing then final polishing with a non-diamond slurry to achieve an epi-ready surface. This process flow involves multiple process tools and is fraught with issues including the need for wafer sorting to group wafers by thickness, manual loading and unloading of wafers, low yields, and unacceptable risk of batch loss (an entire batch of wafers may be scrapped if even one wafer cracks or breaks during process). This paper presents an improved process for single-wafer CMP during SiC substrate manufacturing or backside thinning. In contrast to batch polishing, key improvements include individual wafer processing, fully-automated handling, and elimination of the need for wafer sorting and grouping by thickness. Recent development efforts have achieved removal rates for the 4H Si face up to 2.5 µm/hour for the first step CMP. Removal rates for the C-face can be as much as 3-4x higher consistent with other findings in the industry. Fig 1 shows surface finish after the polishing sequence is complete which is consistently at or below 1 Å Ra as measured by AFM. The combination of an optimized grind followed by an optimized CMP process provides a viable path to both improving wafer yield and reducing costs for SiC wafer manufacturing or backside thinning process sequences. Figure 1