Average Switching Energy Research Articles

Twice‐input variable‐resolution single‐side switching scheme without reset energy for SAR ADC

AbstractA twice‐input variable‐resolution single‐side switching scheme without reset energy is proposed for successive approximation register (SAR) analogue‐to‐digital converters (ADCs). The proposed switching scheme is based on semi‐resting DAC technology to design a four‐array architecture capable of handling twice the swing of the signal input while reducing the capacitor array size. The technique of top‐plate sampling and monotonic shift is utilized so that no switching energy is generated for the first three comparisons. The proposed scheme utilizes full‐capacitor split, bridged switch, and C‐2C dummy capacitor technology, which reduces average switching energy consumption by 99.8% compared to conventional schemes and enables ADC variable resolution function, making the SAR ADC more suitable for IoT applications.

A 10-bit 33.3-kS/s 3.2-fJ/conversion-step single-ended counter-type SAR ADC with dual 5-bit CDAC arrays and counters in 65-nm CMOS

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM.

A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit

In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices, a bridged-switch energy-efficient switching scheme for successive approximation register (SAR) ADCs with a low-complexity capacitor drive circuit is proposed. The technique of top-plate sampling and closed-loop charge recycling is used in the proposed switching scheme so that neither the first nor the second comparison consumes switching energy. The third comparison uses bridge switches to connect the subarray to the main array, effectively reducing switching’s energy consumption. Only the least significant bit (LSB) is dependent on the accuracy of Vcm; thus, the last comparison consumes little switching energy. The proposed switching scheme achieves an average switching energy value of 47.5 CV2ref, which is 96.52% lower than that of the conventional capacitor switching scheme and reduces the area by 75%. The other major circuit modules employed are bootstrapped switches, a fully dynamic comparator, and dynamic SAR logic. The proposed ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in a 9.8-bit effective number of bits (ENOB), a signal-to-noise and distortion ratio (SNDR) of 60.76 dB, a spurious-free dynamic range (SFDR) of 69.85 dB, a power consumption of 14.7 μW, and a figure of merit (FoM) of 16.55 fJ/conv.-step.

Analysis and design of a new shift monotonic switching procedure for SAR ADC

A New Shift Monotonic Switching (NSMS) DAC capacitor array switching scheme suitable for successive approximation register Analog-to-Digital Converters (SAR ADCs) is proposed. The proposed DAC switching scheme utilizes two DAC arrays to achieve double-swing input signals without increasing the size of the capacitor array. In this paper, a 10-bit SAR ADC behavioral-level model is established through detailed analysis of the previously proposed energy-efficient DAC capacitor array switching scheme and the proposed NSMS switching scheme. Compared to the merged capacitor switching (MCS) scheme, the proposed NSMS switching scheme achieves an average switching energy optimization of 88% while maintaining better linearity. Additionally, for low-sampling-frequency applications, an improved SAR ADC architecture based on the NSMS capacitor array switching scheme is provided, which further reduces power consumption and system overhead.

An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative comparator

A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. The proposed scheme synthesizes two reference voltages Vref and Vq to generate relevant voltage levels. The reference voltage Vq is a quarter of the Vref. To ease logic design, the Vref is only utilized during the third phase of conversion with the MSB capacitor of each DAC. The proposed scheme reduces DAC's average switching energy and the area by 94.44 % and 50 % in comparison with the conventional single-ended scheme. Furthermore, a novel 3-stage common-mode insensitive regenerative comparator is proposed to reduce non-linearity errors caused by common-mode voltage variations of DAC. The proposed single-ended ADC is simulated in a standard 65-nm CMOS technology with a resolution of 8-bit and sampling rate of 25 MS/s. The simulation results corroborate that the ADC consumes 124 µW power with 1.2 V supply voltage and attain a 7.23 effective number of bits, resulting in a 33fJ/conversion step FOM.

A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect

A 10-bit-resolution successive approximation ADC with 70-Ms/s conversion rate and with a new configuration for capacitive DAC is represented in this paper. In the DAC structure proposed in this paper, the capacitors that form the Sub-DAC are smaller than the capacitors of the Sub-DAC of the other structures; therefore, the occupied area and the average switching energy in the proposed structure are less than in the other split-array structures, and the proposed structure is less susceptible to parasitic capacitance. Compared to the conventional split-array structure, the total capacitance and Sub-DAC parasitic capacitance are reduced by 15.87% and 46.87%, respectively. Also, the coupling capacitor is a unit capacitor, which improves the capacitor matching in the DAC array furthermore.To design and simulate the proposed 10-bit converter, 180-nm CMOS technology is used. Results of simulation prove that at 70 MS/s operating frequency, with a power supply equal to 1.8 V, and at Nyquist input frequency, SNDR of the proposed converter is 58.26 dB, that means ENOB is 9.39 bit, and SFDR is 64.87 dB. Consequently, the ADC FOM is equal to 123.5 fJ/conversion-step. Also, ramp-test simulation proves that INL and DNL are 0.53/+0.63 LSB and −0.6/+0.6 LSB, respectively. The proposed design consumes 5.8 mw at 70 MS/s operating frequency.

Low-Power Switching Scheme with Quarter Reference Voltage Sources for SAR ADCs

In this paper, an energy-efficient switching scheme with additional quarter-reference voltage sources in a successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for a low power and small area device for frequency modulated continuous wave (FMCW) radar transceivers. Recently, state-of-the-art ADCs have adopted a configuration that also uses Vref/2 as the reference voltage of the ADCs to improve the switching energy of capacitive digital-to-analog converter (CDAC). The proposed switching configuration additionally uses Vref/4 and 3Vref/4 reference voltages as the reference voltage of CDAC. Compared to state-of-the-art configurations that use the additional reference voltage of Vref/2, the average switching energy, and the total capacitance of CDAC in the proposed configuration are reduced by about 87.5% and 50%, respectively. In this switching scheme, the CDAC output voltage gradually converges to Vref/2, like with conventional SAR ADCs, which minimizes the dynamic offset that deteriorates the linearity of the SAR ADC.

A Low Power Fully Differential Level-Crossing ADC With Low Power Charge Redistribution Input for Biomedical Applications

A low-power fully differential level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. Different from conventional ADCs based on the uniform sampling rate, LC-ADC generates fewer samples for biomedical signals and leads to less power consumption in the following blocks. In this design, the power consumption of n-bit DAC and digital parts is reduced significantly with respect to the conventional LC-ADCs. The proposed method uses a charge redistribution block (CRB) instead of the n-bit DAC, which leads to a large reduction in average switching energy. Besides energy-saving, the proposed switching scheme also reduces the complexity of the controlling logic circuit, providing reduced complexity and low power consumption. Another advantage of the proposed LC-ADC is its fully differential structure. As a result, SNDR is improved by decreasing the levels of even harmonics. The proposed LC-ADC is designed in 0.18 um CMOS technology. Post-layout simulation results show an effective number of bits (ENOB) of up to 6.8 bits with about 97-188 nW power consumption under 0.8 V supply voltage and input signal bandwidth from 1 Hz to 4 kHz. The ADC occupies a silicon area of only 60×65 μm2.

Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA. Objectives: The research is focused on efficient area-delay-energy Configurable Logic Block (CLB) design for Field-Programmable Gate Array architecture (FPGA) with successful simulation-based on next-generation technology, Quantum-dot cellular automata. Methods: Each proposed circuit is designed on post CMOS 4 dot 2 electron technology, i.e. QCA (Quantum dot Cellular Automata), is adopted in circuit implementation due to low power dissipation, high clock frequency and high package density. QCADesigner is used to verify the functionality of every circuit. QCAPro tool is used for determining power dissipation. Results: In contrast, a new approach of using de-multiplexer replacing the decoder has been introduced that results in the reduction of the average energy dissipation by almost 57%. A NOR based D flip-flop memory architecture and multiplexer are also used in the lookup table for the configurable logic block. The proposed architecture thus reduces the overall latency. The proposed CLB consists of 6356 QCA cells covering 7.44 um2 area. Write and read latency of proposed CLB are 12 and 7.25 QCA clock, respectively. Conclusion: The present paper concludes that read and write latency reduction occurs; average energy dissipation, leakage, and switching energy dissipation are reduced in a large amount resulting in an advantage of the overall minimization of the latency for the proposed CLB in the process.

Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

PurposeIn nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits.Design/methodology/approachThis paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration.FindingsA new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level.Originality/valueThis paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

A high energy-efficiency and low-area switching scheme for SAR ADCs

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC switches is lower than the conventional and some other methods, which avoids further complicating the logic circuit as well as increasing wiring and area. Moreover, only one voltage source is used as a reference voltage, which makes us needless to have an extra voltage source that must be very accurate.

A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme

This paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications. The input signals are multiplied by two because the dual sampling technique is used during the sampling phase. In this design, a comparator circuit with four input terminals was also applied to implement a fully differential capacitive digital-to-analog converter (CDAC). Simultaneously, by employing an area-efficient and low-energy switching scheme for the capacitive digital-to-analog converter, the average switching energy can be reduced significantly. The proposed design also achieved a reduction in the number of the capacitors and the controlled switches compared with those required in the conventional SAR ADC design. A prototype had been designed and implemented using TSMC 90-nm CMOS 1P9M technology. The measurement results showed that differential nonlinearity and integral nonlinearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively. At a sampling rate of 50-MS/s with a single 1.2-V power supply, the power consumption was $664~\mu \text{W}$ . This design also achieved a signal-to-noise-and-distortion ratio of 57.6 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 5-MHz. The ADC core occupied an active area of $102\times 235\,\,\mu \text{m}^{2}$ .

Design of an Efficient N × N Butterfly Switching Network in Quantum-Dot Cellular Automata (QCA)

Quantum-dot cellular automata (QCA) is a rapidly growing nanotechnology very well suited for designing ultra-dense, low-power, and high-performance digital circuits. In parallel computing, the multistage interconnection network (MIN) provides maximum bandwidth to the components and minimum latency access to the memory modules. Much research has been conducted on CMOS-based MINs for parallel computing. However, the QCA-based switching network is still underexplored. This article proposes a QCA architecture of a new single-layer butterfly switching network (BSN). To achieve this, we design an efficient 2 × 2 switching element (SE), using a modified majority ( $\mathcal{M}{_{[x,y]}}$ ) gate that is fully utilized (i.e., no fixed logic like “0” and “1” at the inputs). The use of a fully utilized majority gate over a partially utilized majority (PUM) one makes the proposed SE more cost-efficient and versatile, and therefore it is used as the building block for designing the switching network. In addition, we deploy the SE to realize 4 × 4 and 8 × 8 BSNs. We also show how the design can be extended for an N × N BSN. All the proposed circuits have been modeled and verified by QCADesigner. QCAPro is used for estimating the average switching and leakage energy dissipation of the proposed circuits. The results show considerable enhancement in terms of cell count, device area, and latency, and thereby outperform all reported prior designs.

Design of QCA-Serial Parallel Multiplier (QSPM) With Energy Dissipation Analysis

This brief presents an efficient single-layer serial-parallel multiplier (SPM) in Quantum-dot Cellular Automata (QCA). We have designed a bit-serial adder (BSA) using a fully utilized majority gate (MV), and a modified E-shaped exclusive-OR (E-XOR) gate. The cell-interactive properties of the QCA cell have been utilized to realize the proposed E-XOR gate. This new gate leads the proposed SPM to achieve a reduction in cell count and area by 30% and 19%, 29% and 24%, 30% and 22%, 32% and 39%, and 36% and 46% for 4-, 8-, 16-, 32-, and 64-bit multipliers, respectively. All proposed circuits have been simulated and verified by using QCADesigner with a coherence vector simulation engine. In addition, the average switching and leakage energy dissipation are estimated using QCAPro tool.

High-efficient two-step switching scheme for SAR ADC with dual-capacitive arrays and four-input comparator

A high energy-efficient and area-saving two-step switching method for the dual-capacitive arrays (DCAs) successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. By adopting two-step architecture, spilt-capacitor method, monotonic switching scheme, four-input comparator and C–2C capacitor array, the proposed procedure achieves 99.84% saving in average switching energy and 84.38% reduction in total capacitance compared to the conventional scheme when applied to a 10-bit SAR ADC, meanwhile achieving DNL and INL only 0.234LSB and 0.281LSB, respectively. Furthermore, this method eliminates reset energy, while achieves a compromise among energy, area, and linearity.

A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique

This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes $3.09~{\boldsymbol{\mu }}\text{W}$ . The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

Energy Efficient Novel Design of Static Random Access Memory Memory Cell in Quantum-dot Cellular Automata Approach

This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% and 15% improvement in terms of total number of Cell counts and Area. Similarly, the proposed design structure realizes the overall power dissipation savings up to 35.3% at maximum energy dissipation of circuit, 38.6% at average energy dissipation of circuit, 36.1% at minimum energy dissipation of circuit, 36.4% at average energy dissipation of circuit and 40.1% at average switching energy dissipation compared to the latest reported designs. The power analysis and structural analysis of the proposed design is compared with its state-of-the-art counterpart designs, using QCAPro and QCADesigner 2.0.3 tools. The proposed QCA based SRAM cell design can be taken as a base design in building an ultra-low power information generating systems like Microprocessors.

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip

A 10-bit 10-KS/s asynchronous successive approximation register (SAR) analogue-to-digital converter (ADC) in 180 nm CMOS process is proposed for low energy wireless senor network chip. Nanowatt power consumption magnitude can be achieved benefiting from the novel switch scheme which can reduce the average switching energy and area of the capacitive digital-to-analog converter (DAC) by 97.66% and 50% without reset energy compared to the conventional approach, respectively. Meanwhile, a cascode current is employed in the subthreshold dynamic comparator to suppress the total offset voltage (mean+3std) variation with the bulk-driven differential pair. As a consequence, the fluctuation of total offset voltage is only 0.28 mV when the input common-mode voltage operates from 200 mV up to 400 mV at 0.4 V supply. Simulation results indicate that a signal-to-noise-plus-distortion ratio (SNDR) of 58.75 dB and a power consumption of 30.4 nW can be achieved at 0.4 V supply voltage and a near Nyquist rate input, resulting in Walden's figure-of-merit (FOMw) of 4.32fJ/conversion-step.

Scaled-down reference switching scheme for low-power SAR ADCs

An energy-efficient scaled-down reference (SDR) digital-to-analogue converter switching sequence is presented for a low-power successive approximation register analogue-to-digital converter. Owing to the fact that the proposed technique utilizes only a quarter of the capacitor array for input sampling, an SDR (Vref/4) and ground (Gnd) for the same input are required for conversion cycles, which achieve reduced switching energy and high linearity. The SDR switching structure improves the efficiency of average switching energy by 99.61% and reduces the total number of required capacitors in the digital-to-analogue converter arrays by 50% compared to the conventional structure.