High-efficient two-step switching scheme for SAR ADC with dual-capacitive arrays and four-input comparator

Abstract

A high energy-efficient and area-saving two-step switching method for the dual-capacitive arrays (DCAs) successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. By adopting two-step architecture, spilt-capacitor method, monotonic switching scheme, four-input comparator and C–2C capacitor array, the proposed procedure achieves 99.84% saving in average switching energy and 84.38% reduction in total capacitance compared to the conventional scheme when applied to a 10-bit SAR ADC, meanwhile achieving DNL and INL only 0.234LSB and 0.281LSB, respectively. Furthermore, this method eliminates reset energy, while achieves a compromise among energy, area, and linearity.