A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip

Abstract

A 10-bit 10-KS/s asynchronous successive approximation register (SAR) analogue-to-digital converter (ADC) in 180 nm CMOS process is proposed for low energy wireless senor network chip. Nanowatt power consumption magnitude can be achieved benefiting from the novel switch scheme which can reduce the average switching energy and area of the capacitive digital-to-analog converter (DAC) by 97.66% and 50% without reset energy compared to the conventional approach, respectively. Meanwhile, a cascode current is employed in the subthreshold dynamic comparator to suppress the total offset voltage (mean+3std) variation with the bulk-driven differential pair. As a consequence, the fluctuation of total offset voltage is only 0.28 mV when the input common-mode voltage operates from 200 mV up to 400 mV at 0.4 V supply. Simulation results indicate that a signal-to-noise-plus-distortion ratio (SNDR) of 58.75 dB and a power consumption of 30.4 nW can be achieved at 0.4 V supply voltage and a near Nyquist rate input, resulting in Walden's figure-of-merit (FOMw) of 4.32fJ/conversion-step.