Average Subthreshold Swing Research Articles

Hf0.5Zr0.5O2-Based Ferroelectric Gate HEMTs With Large Threshold Voltage Tuning Range

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Hr0.5 Zr0.5O2 ferroelectric gate stacks exhibiting significant ferroelectric switching for threshold voltage control are experimentally demonstrated. Ferroelectric gate HEMTs (FeHEMTs) with large threshold voltage tuning range of 2.8 V were obtained, with an on/off ratio of $\sim {10}^{{{5}}}$ based on a GaN-channel HEMT structure suitable for RF applications. Improved subthreshold performance has also been achieved compared to conventional MIS-HEMTs, with reduction in average sub-threshold swing (SSavg) by a factor of 2. As a consequence of the significant ferroelectric polarization achieved on AlGaN/GaN heterostructures, Hr0.5 Zr0.5O2 based ferroelectric gate AlGaN/GaN HEMTs appear promising for nonvolatile and reconfigurable RF and microwave applications.

Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters

A new hetero-structure vertical tunnel field effect transistor is proposed and investigated using Sentaurus Technology Computer-aided Design simulation. Since the direction of the gate electric field is in alignment with the direction of tunneling of electrons, a higher on state current is attained. Optimization of the geometric dimension of the proposed structure is carried out to yield its optimum performance. As temperature variation affects the device performance, temperature analysis of the proposed structure is performed in which both the off state leakage current and the average subthreshold swing increases with temperature. Further investigation on the influence of temperature variation is carried out in terms of Analog/RF parameters such as transconductance, gate capacitance, cut-off frequency, transconductance frequency product and linearity figure of merits. It is observed that the proposed structure attains superior linearity performance and lower distortion at higher gate voltage with rise in temperature and is less affected by temperature variation at lower gate voltage.

A Novel Germanium-Around-Source Gate-All-Around tunnelling Field-Effect Transistor for Low-Power Applications.

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current () (11.9 A), a low OFF-state current () (A), and a low and steady (57.29 mV/decade), with the OFF-state current increasing by times. The GAS GAA TFET has high potential for use in low-power applications.

Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches

The continuous down-scaling of transistors has been the key to the successful development of current information technology. However, with Moore's law reaching its limits, the development of alternative transistor architectures is urgently needed1. Transistors require a switching voltage of at least 60 mV for each tenfold increase in current, that is, a subthreshold swing (SS) of 60 mV per decade (dec). Alternative tunnel field-effect transistors (TFETs) are widely studied to achieve a sub-thermionic SS and high I60 (the current where SS becomes 60 mV dec-1)2. Heterojunction (HJ) TFETs show promise for delivering a high I60, but experimental results do not meet theoretical expectations due to interface problems in the HJs constructed from different materials. Here, we report a natural HJ-TFET with spatially varying layer thickness in black phosphorus without interface problems. We have achieved record-low average SS values over 4-5 dec of current (SSave_4dec ~22.9 mV dec-1 and SSave_5dec ~26.0 mV dec-1) with record-high I60 (I60 = 0.65-1 μA μm-1), paving the way for application in low-power switches.

Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO-=SUB=-2-=/SUB=-/La-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=-/HfO-=SUB=-2-=/SUB=- (HLH) Sandwich Gate Dielectrics

In this paper, the electrical properties of a double-gate dual-active-layer (DG-DAL) thin-film transistor (TFT) is investigated. To increase the ON-current and pixel intensity, and control the voltage stress bias, the conventional gate oxide material (silicon dioxide SiO2) is replaced with a tri-high-k gate dielectric layer, hafnium dioxide HfO2/lanthanum oxide La2O3/hafnium dioxide HfO2 (HLH). Further, the performance of the proposed DG-DAL structure is compared with the single-active-layer (SAL) and dual-active-layer (DAL) TFTs. The amorphous indium-gallium zinc-oxide (a-IGZO) is considered as active layer for SAL channel region, and on the other hand, a-IGZO and indium-tin-oxide (ITO) are considered as active layers for DAL TFT and DG-DAL TFT channel regions. The parameters such as OFF-current, ON-current, ION/IOFF ratio, threshold voltage, mobility, average subthreshold swing, etc. are evaluated for the considered structures. It is observed that the DG-DAL TFT with HLH dielectric offers high ON-current of 3.85·10-3 A/μm, very low OFF-current of 2.53·10-17 A/μm, very high ION/IOFF ratio of 1.51·1014, the threshold voltage of 0.642 V, high mobility of 35 cm2·v-1·s-1 and average subthreshold swing of 127.84 mV/dec. A commercial TCAD simulation tool ATLAS from SilvacoTM is used to investigate all the parameters for considered structures. Keywords: single active layer (SAL), dual active layer (DAL), double-gate dual active layer (DG-DAL), InGaZnO (IGZO), InSnO (ITO), thin-film transistor (TFT), HfO2/La2O3/HfO2 (HLH).

A non-uniform silicon TFET design with dual-material source and compressed drain

Tunnel FET is the well-built candidate in the field of low-power ICs mainly because of its lower subthreshold swing (SS). But its ON current is relatively small and ambipolar current is high. The advantage of having a lower SS does not hold for higher gate voltages, which leads to higher average SS. In this paper, for the first time, a non-uniform channel with double-material source and compressed drain TFET structure is introduced. The simulation results show that the proposed structure has a minimum point SS of 9 mV/decade and an average SS of 22 mV/decade for a wide range of gate voltages. In addition, the ambipolar current, ON current, and OFF current are obtained to be 10−14 A/μm, 10−5 A/μm, and 10−16 A/μm, respectively, which lead to a remarkable value of the ON–OFF current ratio of about 1011. The effects of trap charge at oxide/semiconductor interface for different trap charge distributions have been investigated. Finally, it is observed that as compared to uniform distribution traps, Gaussian distribution traps degrade the characteristics in terms of ON–OFF current ratio and SS.

Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor

In this paper, using device simulations, we investigate electrical characteristics of a tunnel field-effect transistor (TFET) in which band-to-band tunneling (BTBT) occurs dominantly within the channel, rather than at source-channel junction. The within-channel BTBT is enabled by sharp band-bending induced by the dual material gate (DMG). The work-functions of two metal gates are chosen, such that the surface potential profile exhibits a distinct step at the DMG interface. Consequently, even under equilibrium condition, a high lateral electric field and an abrupt tunneling junction exist at the DMG interface. When a small gate voltage is applied, the inherent lateral electric field aids in creating an abrupt band alignment and obtaining a small tunneling width. As a result, an excellent average subthreshold swing is obtained in the proposed device. We have also investigated scaling of channel lengths in the proposed device and have demonstrated that within-channel tunneling can be exploited for channel lengths of 40nm and above. Furthermore, low drain threshold voltage and suppressed drain-induced barrier lowering can be obtained in the proposed device. Moreover, in contrast to conventional TFETs, electrical characteristics of the proposed device are less susceptible to source doping variations and shift in gate-edge with respect to the source-channel junction.

Improvement in Electrical Characteristics of ZnSnO/Si Bilayer TFET by W/Al₂O₃ Gate Stack

We have examined impacts of gate insulator (Al2O3 or HfO2) and gate electrode (TiN or W) on electrical performance of ZnSnO/Si bilayer tunneling fieldeffect transistors (TFETs). It is found from the capacitance-voltage ( ${C}$ - ${V}$ ) characteristics that the W gate is effective to reduce the counter-clockwise hysteresis. Additionally, the optimal temperature of post-metallization annealing (PMA) is different for each gate stack, and this optimization is critically important for the high ON-state current ( ${I} _{\mathrm{ ON}}$ ) and steep ON/OFF switching. The W/Al2O3/ZnSnO/Si bilayer TFET provides the hysteresis-free steep ON/OFF switching with the minimum sub-threshold swing ( SS ) of 65.4 mV/dec. and average SS of 72.0 mV/dec. in a gate-voltage swing of 0.3 V, which are 19% and 18% lower than the control TiN/Al2O3/ZnSnO/Si bilayer TFET. When the gate stack is replaced by W/HfO2/Al2O3, the TFET exhibits less steep ON/OFF switching in spite of thinning capacitance equivalent thickness (CET) from 5.9 and 2.3 nm. These results indicate the importance of improvement in the gate stack quality on the sub-threshold characteristics of the bilayer TFETs.

Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40 μA/μm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with V DS = V GS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressed at the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decade was obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.

Robust Impact-Ionization Field-Effect Transistor Based on Nanoscale Vertical Graphene/Black Phosphorus/Indium Selenide Heterostructures.

Maintaining the rapid development of information technology by scaling down a metal-oxide semiconductor field-effect transistor faces two serious challenges. First, the gate field loses control of the channel as it continuously decreases. Second, the fundamental thermionic limit restricts the reduction in supply voltage. Thus, further scaling down necessitates alternative device structures and different switching mechanisms. Here, we report impact-ionization transistors (IITs) based on nanoscale (∼30 nm) vertical graphene/black phosphorus (BP)/indium selenide (InSe) heterostructures. By facilitating the carrier multiplication of the ballistic impact-ionization process as the internal gain mechanism in sub-mean-free-path (sub-MFP) channels, the IITs exhibit a low average subthreshold swing (SS < 1 mV/dec) over five current levels. High stability (>10 000 cycles) and small hysteresis (<1%) switching properties are also obtained. The experimental demonstration of such transistor combining steep SS, high ON-state current density, reliable robustness, miniature footprint, and low bias voltage approaches fulfillments of targets for next-generation devices in the International Technology Roadmap for Semiconductors.

F-Shaped Tunnel Field-Effect Transistor (TFET) for the Low-Power Application.

In this report, a novel tunnel field-effect transistor (TFET) named ‘F-shaped TFET’ has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As a result, it is compared to an L-shaped TFET, which is a motivation of this work, the F-shaped TFET can lower turn-on voltage (VON) maintaining high on-state current (ION) and low subthreshold swing (SS) with the help of electric field crowding effects. The optimized F-shaped TFET shows 0.4 V lower VON than the L-shaped TFET with the same design parameter. In addition, it shows 4.8 times higher ION and 7 mV/dec smaller average SS with the same VON as that for L-shaped TFET.

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 &lt; ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

In this article, we propose a novel nanotube (NT) tunneling field-effect transistor with a core source (CSNT-TFET) which uses line tunneling. We systematically investigate the CSNT-TFET with the help of calibrated 3-D simulations and demonstrate that it outperforms the conventional NT-TFET in terms of both static and dynamic performance. We show that the CSNT-TFET exhibits a reduced average subthreshold swing (SS) of 33 mV/decade with Ge-source for more than eight orders of magnitude of drain current at an ultralow supply voltage ( ${V}_{\text {DS}}= {0.3}$ V). In addition, the ON-state current of the CSNT-TFET is enhanced by ~13 times with Si-source and by ~6 times with Ge-source even at ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V when compared with the NT-TFET. Without the use of any exotic material for the source and channel regions, the CSNT-TFET offers an impact ionization MOS-like steep SS (a minimum SSpoint of ~1 mV/decade) and a high ON-state current of ~10−6 A for ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V. Furthermore, the impact of the gate sidewall spacer and source diameter on the performance of the CSNT-TFET is also investigated.

Investigation of a Ge-Source Vertical TFET With Delta-Doped Layer

In this article, a $\delta $ -doped germanium-source vertical TFET (Ge-source vTFET) is proposed and investigated by Synopsis TCAD simulation. Higher ON-state current is obtained as the electron tunneling takes place in a direction parallel to the gate electric field. The incorporation of the $\delta $ -doped layer in the germanium source region further reduces the OFF-state leakage current. The impact on the variation of the device geometric dimensions has been studied for various electrical parameters and the dimensions are optimized accordingly through extensive simulations. A very high current ratio of the order ~1011 with a substantially low average subthreshold swing of 21.2 mV/decade is achieved. Benchmarking of the proposed Ge-source vTFET with other novel TFETs is carried out which produced better results in terms of high ON -state current and SSavg. The results obtained for the proposed vTFET make it a potential candidate for ultralow-power applications.

Comparative study of InGaN and InGaAs based dopingless TFET with different gate engineering techniques

In this paper, we have presented the comparative analysis of InGaN and InGaAs based DL TFETs with different gate engineering methods for lowering the sub-threshold swing and increasing the ION/IOFF ratio. The 2D simulation study is carried out for comparing the results of conventional DL TFET with three gate engineered structures. InGaAs doped hetero-dielectric hetero-gate DL TFET shows best result of about ~2.217 times increase in the ION/IOFF, 40.17% decrease in the average sub-threshold swing as compared to their respective DL TFET structure. Similarly, InGaN doped HD-HG DL TFET shows ~8.514 times increase in the ION/IOFF, 45.83% decrease in the average sub-threshold swing as compared to their respective DL TFET structure. Finally the result shows InGaAs based HD-HG DL TFET as a favourable device for low power and digital applications.

Van der Waals negative capacitance transistors

The Boltzmann distribution of electrons sets a fundamental barrier to lowering energy consumption in metal-oxide-semiconductor field-effect transistors (MOSFETs). Negative capacitance FET (NC-FET), as an emerging FET architecture, is promising to overcome this thermionic limit and build ultra-low-power consuming electronics. Here, we demonstrate steep-slope NC-FETs based on two-dimensional molybdenum disulfide and CuInP2S6 (CIPS) van der Waals (vdW) heterostructure. The vdW NC-FET provides an average subthreshold swing (SS) less than the Boltzmann’s limit for over seven decades of drain current, with a minimum SS of 28 mV dec−1. Negligible hysteresis is achieved in NC-FETs with the thickness of CIPS less than 20 nm. A voltage gain of 24 is measured for vdW NC-FET logic inverter. Flexible vdW NC-FET is further demonstrated with sub-60 mV dec−1 switching characteristics under the bending radius down to 3.8 mm. These results demonstrate the great potential of vdW NC-FET for ultra-low-power and flexible applications.

An In0.53Ga0.47As/In0.52Al0.48As Heterojunction Dopingless Tunnel FET With a Heterogate Dielectric for High Performance

In this paper, an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As heterojunction dopingless tunnel field-effect transistor (HDL-TFET) with an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> heterogate dielectric is proposed, where the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -pocket with variable electron concentration can be formed by adjusting the length of source-side channel (LSC) based on the charge plasma concept, instead of employing conventional ion implantation or dual-material gate techniques. It aims to improve the device performance and simplify the device fabrication. At the drain bias of 0.3 V, numerical simulations show that the on-state current (ION) of the HDL-TFET with LSC = 4 nm can approach ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A/μm that is far higher than that of the Si-DL-TFET (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/μm), and the average subthreshold swing (SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> ) can approach 36.6 mV/decade that is significantly lower than that of the Si-DL-TFET (89.2 mV/decade). It is also found that the drain-induced barrier lowering (DIBL) effect and the ambipolar current can be effectively suppressed in the HDL-TFET because of an existence of heterojunction. Under the condition of low gate and drain biases, the HDL-TFET exhibits peak values of the cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and the maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) approaching 13 and 4.73 GHz, respectively, while the Si-DL-TFET yields those of 8.05 and 2.26 GHz, respectively, under relatively higher biases. It indicates that the HDL-TFET is a promising device for low-power consumption radio frequency applications.

Nanowire-Seeded Growth of Single-Crystalline (010) β-Ga2 O3 Nanosheets with High Field-Effect Electron Mobility and On/Off Current Ratio.

2D β-Ga2 O3 nanosheets, as fundamental materials, have great potential in next generations of ultraviolet transparent electrodes, high-temperature gas sensors, solar-blind photodetectors, and power devices, while their synthesis and growth with high crystalline quality and well-controlled orientation have not been reported yet. The present study demonstrates how to grow single-crystalline ultrathin quasi-hexagonal β-Ga2 O3 nanosheets with nanowire seeds and proposes a hierarchy-oriented growth mechanism. The hierarchy-oriented growth is initiated by epitaxial growth of a single-crystalline β-Ga2 O3 nanowire on a GaN nanocrystal and followed by homoepitaxial growth of quasi-hexagonal (010) β-Ga2 O3 nanosheets. The undoped 2D (010) β-Ga2 O3 nanosheet field effect transistor has a field-effect electron mobility of 38 cm2 V-1 s-1 and an on/off current ratio of 107 with an average subthreshold swing of 150 mV dec-1 . The from-nanowires-to-nanosheets technique paves a novel way to fabricate nanosheets, which has great impact on the field of nanomaterial synthesis and growth and the area of nanoelectronics as well.

Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling

The dopingless tunneling FET (DLTFET) has attracted more and more attention due to the reduction of process complexity comparing to traditional TFET with heavy doping source and drain regions. But the on-state current of conventional DLTFET is lower because its on-state current is only determined by point tunneling (PT) between source and channel. In this work, a new dual-gate DLTFET based on line tunneling (LT) is designed and studied by Sentaurus TCAD simulation tool. The on-state current and subthreshold swing (SS) of DLTFET are greatly improved by skillfully designing back gate engineering and bias. Applying this novel design, the line tunneling is created from channel bottom to channel top, which dramatically enhances tunneling area and tunneling current. So the on-state current of LT_DLTFET consists of point tunneling between source and channel as well as line tunneling in channel region. Comparing to the traditional PT_DLTFET based on Ge, the simulation results reveal that the on-state current of LT_DLTFET based on Ge is increased to 14.8μA/μm from 6.5μA/μm at Vg=1V and Vd=0.5V, and the average SS and minimum SS are decreased to 22.9mV/dec and 6.5mV/dec from 33.9 mV/dec and 9.5mV/dec, respectively. The LT_DLTFET is also proper to both Si and III-V materials. This design greatly promotes the application potential of DLTFET.

High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET.