Average Propagation Delay Research Articles

N-DIBL optimization of NC-GAAFET NW for low power fast switching applications

Gate-all-around field effect transistors (GAAFETs), exhibit improved SCEs, are proposed to replace conventional FinFET in scaled nanodevices owing to excellent gate control. The voltage scaling concept is embodied in negative capacitance (NC) which provides same on current at reduced voltage. The proposed NC-GAAFET yields 5.31 times larger ION and IOFF is significantly reduced by ⁓105 orders, which is due NC effect, compared to baseline NW. SSavg for the NC-GAAFET is 33mV/dec which surpasses Boltzmann tyranny and manifests steep subthreshold behavior. Effect of FE thickness (tfe) variations on DIBL has been explored and found to be negative, which improves SCEs. The negative-DIBL for device has been found to be −20 mV/V at tfe = 6 nm. Furthermore, a CMOS inverter circuit employing the NC-GAAFET has been presented that provides an average propagation delay of 174 fS which is 47 % lesser as compared to that of baseline device. The NC-GAAFET NW findings fulfill the quest of low power fast switching device for digital applications.

Comparative Analysis of CMOS-based D-type Flip-Flop Architectures for High-Performance VLSI Applications Using 45-nm CMOS Technology

High performance VLSI (very large-scale integration) is an essential electronic technology required for space missions and scientific advancements. The only source of reliance for the VLSI designer is the data storage devices designated as flip-flops, which are widely used in semiconductor memory devices as well as for data processing and storage in the telecommunication fields. In this paper, the four D-type flip-flop architectures of CMOS-based D-type flip-flops, such as D-type flip-flops using traditional technology (DFF-T), D-type flip-flops with Demorgan’s law (DFF-DL), D-type flip-flops with transmission gates (DFF-TG), and D-type flip-flops with five transistors (DFF-F), have been designed and constructed. The analytical simulations of the schematics and equivalent layouts of these four architectures are implemented using 45-nm complementary metal-oxide-semiconductor (CMOS) technology. With cadence virtuoso design software, the performance investigation of the four D-type flip-flop architectures is compared in terms of layout area, transistor counts, average power consumption, rise time, fall time, and propagation delay. The DFF-F technologies have modestly compact design goals in order to reduce production costs and achieve faster processing speeds with fewer transistors.

A rail-to-rail high speed comparator with LVDS output in 0.18-[formula omitted]m SiGe BiCMOS Technology

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level VC, the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator’s gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator’s output is transmitted at high speed through an LVDS interface. This design is implemented using 0.18μm SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns.

Impact of Parametric Variation on the Characteristics and Performance of CNTFET Inverter

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter.

Effect of curie temperature on electrical parameters of NC-FinFET and digital switching application of NC-FinFET

Power consumption of the device enhances as temperature rises, degrading the performance of conventional MOSFET. In the present paper the performance parameters of proposed (NC-FinFET) device has been found to be improved with the rise in temperature compared to baseline FinFET. The simulation is carried out in Sentaurus TCAD and several electrical characteristics are extracted. The results are explained on the basis of Landau theory, with the incorporation of 5 nm FE layer in the gate stack. Mathematical modeling of electrical parameters like drain current (Ids), threshold voltage (Vth), transconductance (gm) and subthreshold swing (SS) has been done to incorporate the effect of temperature considering the ferro and paraelectric phase. The said parameters have been investigated for temperature variations from 250 to 500 K, in ferroelectric and paraelectric phases that are distinguished through the Curie temperature (Tc = 460 ± 10 K). The Vth and SS show a non linear nature at T < Tc and linear behavior T > Tc. The transconductance shows peak value at Tc. Finally, the proposed NC-FINFET is utilized to realize an inverter. The proposed inverter design shows a better performance matrix interms of average propagation delay (tp) as compared to baseline Complementary FINFET inverter.

High Performance Energy-Efficient Leakage-Tolerant Dual Keeper Pseudo Domino Logic

In this paper, an improved high performance energy-efficient leakage-tolerant dual keeper pseudo domino logic circuit is proposed. Circuit design methodologies such as pseudo domino, stacking effect and inverted clock-controlled dual keeper are used in the proposed work for significant reduction of the circuit’s propagation delay and leakage current. Using pseudo-domino logic voltage swing at the output is reduced, stacking effect reduces the leakage current and charge sharing issues in the circuit are reduced by an inverted clock-controlled dual keeper circuit. Leakage current in the proposed circuit is decreased by 21.9%, 20.8%, 71.6%, 52.4% and 57.5% to the conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic, respectively at a 27°C temperature and 1GHz clock frequency. Similarly, delay in the proposed circuit is reduced by 83.3%, 80.1%, 89.8%, 81.3% and 81.5% in comparison to conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic circuit, respectively. Performance metrics like power dissipation, delay, PDP, leakage current, static power, and EDP of the proposed circuit are analysed and compared with the existing domino logics. Monte-Carlo simulation is performed using 1000 samples to analyse the performance of the proposed circuit. The proposed logic circuit is also tested against temperature and process variations. The median values of the proposed buffer circuit’s power and delay are 5.6µW and 1.28ps, respectively and the standard deviation of average power and propagation delay are 633.62nW and 84.37fs, respectively at 27°C and 1GHz clock frequency.

Novel design of power-efficient quaternary logic gates using CNTFET

ABSTRACT This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs.

QoE-Aware Efficient Content Distribution Scheme For Satellite-Terrestrial Networks

The satellite-terrestrial networks (STN) utilize the spacious coverage and low transmission latency of the Low Earth Orbit (LEO) constellation to transfer requested content for subscribers especially in remote areas. With the development of storage and computing capacity of satellite onboard equipment, it is considered promising to leverage in-network caching technology on STN to improve content distribution efficiency. However, traditional caching and distribution schemes are not suitable in STN, considering dynamic satellite propagation links and time-varying topology. More specifically, the unevenness of user distribution heightens difficulties for assurance of user quality of experience. To address these problems, we first propose a density-based network division algorithm. The STN is divided into a series of blocks with different sizes to amortize the data delivery costs. To deploy the caching satellites, we analyze the link connectivity and propose an approximate minimum coverage vertex set algorithm. Then, a novel cache node selection algorithm is designed for optimal subscriber matching. On the basis of time-varying network model, the STN cache content updating mechanism is derived to enable a stable and sustainable quality of user experience. The simulation results demonstrate that the proposed user-oriented STN content distribution scheme can obviously reduce the average propagation delay and network load under different network conditions and has better stability and self-adaptability under continuous time variation.

Empirical Comparison of Block Relay Protocols

Block relay protocols play a key role in the performance and security of public blockchains. As a result, several such protocols have been deployed in the context of Bitcoin and its variants (e.g. legacy, compact block relay and Graphene) in an attempt to reduce bandwidth utilization. However, the relative performance of these protocols in realistic networking conditions (e.g. with nodes churning -joining and leaving the network) is still not known. This paper aims to fill this key knowledge gap using an experimental testbed of twelve full nodes connected to the Bitcoin Cash blockchain. With the aid of novel logging tools, we contrast the performance of these three protocols, in realistic scenarios, with respect to communication, delay, and block decoding success. Our main findings are that Graphene generally performs the best when nodes remain connected, boasting an average propagation delay of 190 ms (i.e. 29% lower than compact block and 80% lower than the legacy protocol). However, when nodes churn at a high rate, compact blocks may perform better. Through a careful temporal analysis, we identify some root causes of the protocol inefficiencies, together with potential mitigation. We have made our measurement framework and experimental logs publicly available to the broader research community.

INTERLINK: A Digital Twin-Assisted Storage Strategy for Satellite-Terrestrial Networks

Recently, low-orbit satellite networks have gained lots of attention from the society due to their wide coverage, low transmission latency, and storage and computing capacity. Providing seamless connectivity to users in different areas is envisioned as a promising solution, especially in remote areas and for marine communication. However, when jointly used with terrestrial networks composing satellite-terrestrial networks, the satellite moving speed is much faster than the ground terminal, which can cause inconsistent service from a single satellite, and therefore lead to frequent satellite handover. Moreover, due to the dynamic and time slot visibility of satellites, the topology of an intersatellite changes frequently, which results in loops during satellite handover, thereby reducing the utilization of links. To address these problems, we propose a digital twin-assisted storage strategy for satellite-terrestrial networks (INTERLINK), which leverages the digital twins (DTs) to map the satellite networks to virtual space for better communication. Specifically, we first propose a satellite storage-oriented handover scheme to minimize the handover frequency by considering the limited access time and capacity constraints of satellites. Then, a multiobjective optimization problem is formulated to obtain the optimal satellite by genetic algorithm. Finally, considering the timing visibility of the satellite links, a digital twin-assisted intersatellite routing scheme is introduced to improve the quality of data delivery between satellites. Simulation results demonstrate that the proposed INTERLINK can reduce both handover times and average propagation delay compared with its counterparts. Meanwhile, benefitting from integrated DT, both the quality of data delivery and the delay of intersatellite links are considerably improved.

Implementation of Marin Predators Algorithm for optimizing the position of multiple Optical Network Units in Fiber Wireless Access Networks

• The problem of the optimal placement of multiple ONUs in FiWi networks is solved using- Marin predators algorithm (MPA) • A cost function is defined in terms of the average distance among ONUs and users. • The optimized locations are used in a developed simulation model to analyze the performance of FiWi network in terms of throughput and average propagation delay of FiWi access network. • The results obtained through the MPA are benchmarked with respect to the Harris Hawks Optimization (HHO), Whale Optimization algorithm (WOA), Moth-Flame optimization (MFO) and Greedy algorithms. Fiber-Wireless (FiWi) access network is a hybrid network that offers huge bandwidth and ubiquity to the users and is expected to play a dominant role in the emerging next generation communication networks. In this manuscript, a novel Marine Predators algorithm (MPA) is used to optimally place multiple Optical Network Units (ONUs) in FiWi access network. The optimized locations are used in a developed simulation model to assess the performance of FiWi network in terms of throughput and average propagation delay considering peer-to-peer communication. Also, the optimizer’s performance was evaluated in terms of fitness value, exploration, exploitation, computational complexity and nature of convergence curve. The MPA's efficiency is benchmarked with respect to a heuristic, Greedy algorithm, as well as existing efficient metaheuristics – Moth-Flame Optimization (MFO), Whale Optimization algorithm (WOA) and Harris-Hawks Optimization (HHO). It was found that MPA outperforms Greedy, MFO, WOA and HHO algorithms in each of the cases.

Performance Comparison of CMOS and NMOS GNRFET Full Adder

Transistor makes up the cornerstone of modern computing. In this work, a SPICE model of GNRFET was used to simulate the performance of a NMOS and CMOS binary full adder. The performance of this adder was evaluated in terms of its average power consumption and propagation delay. Three variables, namely the resistance value, dimer lines and channel length were manipulated and the impact on its performance was assessed. It was observed that a linear improvement in propagation delay was accompanied by an exponential increase in power consumption and only a small range of values of resistance was able to deliver a relatively reasonable trade-off between power consumption and propagation delay. These values range from approximately 110 kΩ to 130 kΩ. When the dimer lines were varied from 12 to 8 and channel length was varied from 32 nm to 16 nm, the results showed that a channel length of 16 nm was superior to that of a channel length of 32 nm as it showed 25.25 % of improvement in propagation delay at approximately similar power consumption. On the other hand, the choice of dimer lines and circuit architecture was required to be evaluated on a case-by-case basis. For a compute-intensive application with a controlled environment, NMOS logic with 8 dimer lines should be chosen, while for less compute-intensive applications and portable devices, CMOS logic with 12 dimer lines should be utilised. A NMOS logic was chosen for the former due to a reasonable trade-off of 30.94 % of power consumption for a 35.03 % of propagation delay was established When the performance of these full adders are compared to that of a MTGB based ternary gate in terms of their performance, it was found that the CMOS and NMOS logic full adder performed better than a MTGB based ternary full adder.

Link assignment based on vertex deleting using adjacency matrix for LEO optical satellite network

In the LEO optical satellite network (OSN), each satellite has more than a dozen potential links, but the number of onboard terminals is limited. The beam divergence angle of optical satellite communication is extremely small, so only one bidirectional communication link can be established between a pair of communication terminals, therefore how to use limited onboard communication terminals to establish inter-satellite links (ISLs) for each satellite to achieve high-efficiency communication is an urgent problem to be solved. However, previous studies on link assignment schemes cannot take into account the terminal utilization ratio and the small end-to-end delay of the network. To solve the above-mentioned link assignment problem, this paper proposes the link assignment scheme based on vertex deleting using adjacency matrix (VDAM-LAS) for the first time. This scheme can ensure that any number of communication terminals on each satellite can be used to establish ISLs and the smaller network delay and ISLs hops can be obtained. In addition, it solves the link assignment problem of the OSN with the limit of the maximum allowable link hops of a single satellite, which is a problem that cannot be optimized using the previous LASs. The simulation results show that when assigning incessant ISLs, compared with the Manhattan Street Network (MSN)-LAS, greedy-LAS and perfect match model (PMM)-LAS, the average hops are reduced by 8.87%, 3.13%, 0.49%, respectively, and the average propagation delay is reduced by 17.24%, 2.86%, 0.8%, respectively. When assigning intermittent ISLs, the average hops are reduced by 10.45% and 6.89%, respectively, compared with the greedy-LAS and PMM-LAS.

An ultra-low leakage and small-area level shifter based on super-cut-off mechanism

In this paper, a novel level shifter design with ultra-low leakage power and an extremely compact area is proposed. The presented structure is composed of an input inverter, a Wilson-like current mirror, and an output inverter. To minimize the leakage power, a super-cut-off pull-down network and a stacked pull-up network are proposed in our structure. Moreover, the novel architecture employs the multi-threshold CMOS (MTCMOS) and sizing technology to minimize the layout area. The prototype has been fabricated by the SMIC 55 nm MTCMOS technology with an area of 5.614 μ m 2 . Experimental results show that the average leakage of our level shifter is extremely 21.62 pW low power when converting a 0.3 V input to 1.2 V output. At the same time, the average propagation delay and the average energy per transition of the presented structure are 24.06 ns and 4.42 fJ, respectively.

Dynamic and Optimized Routing Approach (DORA) in Vehicular Ad hoc Networks (VANETs)

Vehicular Ad hoc Networks (VANETs) are one of the significant areas of research and this is also a subfield in Ad Hoc Networks. This is mainly focused on improving the safety of roads and reducing the total number of accidents. There is no central coordination to this network, nodes are mobile, dynamic topology, the routing process is a big challenge, and this is most responsible for the delivery message to the small overhead and delay. Routing is a tedious task that occurs huge changes in network topology and delivers the data packets in a limited period. In VANETs many existing routing protocols are introduced to overcome various issues but these are not efficient to overcome all the issues in routing. Routing shows a huge impact on other parameters such as data transmission rate (DTR), packet delivery ratio (PDR), Packet Drop Ratio (PDRatio), Average Propagation Delay (APD) and throughput. In this paper, the dynamic and optimized routing approach (DORA) is introduced in VANETs to overcome the various issues and improve the performance of IP by measuring the DTR, PDR and PDRatio. Comparisons among the Ant Colony Optimization (ACO), improved distance-based ant colony optimization routing (IDBACOR), and DORA is shown.

Design of an Efficient Memristor-based Dynamic Exclusive-OR gate.

In this paper, an efficient memristor-based dynamic logic design for an Exclusive-OR gate is proposed. The proposed realization reduces the number of cascaded stages and component count thereby providing an overall performance improvement. The performance of the proposed design is compared with the most recent existing design through LTspice software simulations at 32 nm technology node in terms of total power consumption, average propagation delay, and number of components used in the implementation. The outcomes depict that the proposed design consumes 57 % reduced power and provides faster operation with 5.09 % improvement in propagation delay in comparison to its existing counterpart. Further, the robustness of the proposed design is verified by performing technology and capacitance variation. The results show the impeccable performance of proposed design across different load capacitance and technology nodes.

Optimized Traffic Grooming through modified PSO based Iterative Hungarian algorithm in Optical Networks

Due to huge size of the data and quick transmission of data between the nodes present in the optical network, a condition of network traffic is created among the nodes of the network. This issue of traffic can be overcome by employing numerous traffic grooming techniques. In this research paper, the best suitable shortest path is determined by the multi objective modified PSO algorithm and an innovative visibility graph based Iterative Hungarian Traffic grooming algorithm is implemented to reduce the blocking ratio through improving the allocation of bandwidth between the users. Then finally the performance analysis is carried out by means of performance measures such as traffic throughput, transceivers count, average propagation delay, blocking ratio, and success ratio. It can be inferred that the proposed work obtains enhanced outcomes when compared to the other existing techniques.

Performance-aware placement and chaining scheme for virtualized network functions: a particle swarm optimization approach

Network functions virtualization (NFV) is a new concept that has received the attention of both researchers and network providers. NFV decouples network functions from specialized hardware devices and virtualizes these network functions as software instances called virtualized network functions (VNFs). NFV leads to various benefits, including more flexibility, high resource utilization, and easy upgrades and maintenances. Despite recent works in this field, placement and chaining of VNFs need more attention. More specifically, some of the existing works have considered only the placement of VNFs and ignored the chaining part. So, they have not provided an integrated view of host or bandwidth resources and propagation delay of paths. In this paper, we solve the VNF placement and chaining problem as an optimization problem based on the particle swarm optimization (PSO) algorithm. Our goal is to minimize the required number of used servers, the average propagation delay of paths, and the average utilization of links while meeting network demands and constraints. Based on the obtained results, the algorithm proposed in this study can find feasible and high-quality solutions.

Churn in the Bitcoin Network

Efficient and reliable propagation of blocks is vital to the scalability of the Bitcoin network. As a result, several schemes, such as the compact block protocol (BIP 152), have been proposed over the last few years to speed up the block propagation. Even so, we provide experimental evidence that (i) the vast majority (97%) of Bitcoin nodes exhibit only intermittent network connectivity ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i.e.</i> , churn), and (ii) this churn results in significant number of unsuccessful compact blocks, roughly three times the statistic for continuously connected nodes. We conduct experiments on the Bitcoin network that show that churn results in a roughly five fold increase in block propagation time ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i.e.</i> , 566.89 ms vs. 109.31 ms) on average. To effect our analysis, we develop a statistical model for churn, based on empirical network data, and use this model to actuate live test nodes on the Bitcoin network. The performance of the system is measured within a novel framework that we developed for logging the internal behavior of a Bitcoin node, and which we share for public use. Finally, to mitigate the problem of missing transactions in churning nodes, we propose and implement into Bitcoin Core a new synchronization protocol, dubbed MempoolSync. Our measurements show that churning nodes implementing MempoolSync experience significantly better performance than standard nodes not implementing MempoolSync, including average block propagation delay reduced by over 50%.

An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

The increasing number of voltage domains along with the size of the data bus requires an exponential increase in the number level shifter (LS) circuits for signal interfacing, creating an exploding in silicon area and power consumption. Higher area-efficiency can be attained by further improving the integration density of the LS circuit. In this paper, we present a multi-function ultra-low-voltage LS with re-configurable logic with embedded time-borrowing latch. The proposed circuit is implemented on CMOS 45nm technology. It is capable of converting the input voltage of 0.3 V to an output voltage of 1.8 V with an input frequency of 1 MHz. The proposed architecture has achieved a superior area efficiency with reduced transistors number of $2.4\times $ and reduced power delay product (PDP) of $4.65\times $ compared with its discrete logic block level implementation when the input voltage, output voltage, and the input frequency are 0.3 V, 1.8 V, and 1 MHz, respectively. The average propagation delay and power consumption are 52.7 ns and 34.6 nW, respectively.