Abstract
In this paper, a novel level shifter design with ultra-low leakage power and an extremely compact area is proposed. The presented structure is composed of an input inverter, a Wilson-like current mirror, and an output inverter. To minimize the leakage power, a super-cut-off pull-down network and a stacked pull-up network are proposed in our structure. Moreover, the novel architecture employs the multi-threshold CMOS (MTCMOS) and sizing technology to minimize the layout area. The prototype has been fabricated by the SMIC 55 nm MTCMOS technology with an area of 5.614 μ m 2 . Experimental results show that the average leakage of our level shifter is extremely 21.62 pW low power when converting a 0.3 V input to 1.2 V output. At the same time, the average propagation delay and the average energy per transition of the presented structure are 24.06 ns and 4.42 fJ, respectively.
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