Average Propagation Delay Research Articles

Comparator with Completion Signal

This note provides a design of a binary comparator with completion signal. The average propagation delay is a constant, independent of n, the number of inputs, while the logic complexity is a linear function of n.

STL versus ISL: an experimental comparison

Schottky-transistor logic (STL) and integrated Schottky logic (ISL) have been fabricated in both 4-/spl mu/m and 2-/spl mu/m oxide isolated processes and characterized over the military temperature range (-55 to +125/spl deg/C ambient). The temperature coefficient of the average propagation delay (t/spl tilde//SUB pd/) is positive for STL over the entire operating current range. For ISL, the temperature coefficient of t/SUB pd/ is negative at low currents and positive at high currents. Both the 4-/spl mu/m and 2-/spl mu/m ring oscillator designs studied showed this behavior. At 25/spl deg/C, t/SUB pd/ data indicate no difference between STL and ISL for practical purposes. At -55/spl deg/C, the STL has a slight (~0.1 ns) speed advantage over ISL. At 150/spl deg/C (junction), the 2-/spl mu/m STL gates with a 200 /spl Omega///spl square/ base sheet resistance have the lowest minimum t/SUB pd/ of the gates studied (0.9 ns at a total current of 190 /spl mu/A) compared to the best for ISL at 1.0 ns and 150 /spl mu/A. The ISL operates at a lower logic swing than the STL at 105/spl deg/C, and has a speed advantage in the current range useful for VLSI. Additional data are presented which demonstrate the effect of the base resistance, epitaxial resistivity and substrate resistivity on delay.

A GaAs low-power normally-on 4-bit ripple carry adder

The realization and performance of a low-power buffered FET logic (1p-BFL) 4 bit ripple carry adder is reported. Performance measurements indicate a critical path average propagation delay of 1.9 ns at a total power dissipation of 45 mW, output buffers included (27 mW without). This corresponds to an average propagation delay of 380 ps/gate (FI/FO=/SUP 5///SUB 3/), an average power consumption of 1.56 mW/gate, and a power-delay product of 0.6 pJ. Best speed performance biasing conditions yield a 1.25 ns critical path average propagation delay at a total power dissipation of 180 mW (180 mW excluding buffers), which corresponds to an average gate delay, power consumption and power-delay product of 250 ps, 6 mW, and 1.5 pJ, respectively. Standard cell layout techniques yield an average gate density of 200 gates/mm/SUP 2/, interconnection wiring included.

Recent Advances in GaAs Digital IC Technology

Interest in the GaAs digital integrated circuit technology is growing at a rapid pace. In this paper a comparative analysis of the GaAs FET technology and Si technologies is made. Recent developments at our laboratory are discussed. These include: (1) The implementation of the processing of 3 inch diameter wafers, which brings GaAs fabrication in line with standard semiconductor precessing; (2) Data on the performance of frequency divider circuits showing operation at clock rates as high as 2.6 GHz for a simple D-flip-flop architecture (equivalent to 77 ps average NOR gate propagation delay), and showing excellent performance over a wide temperature range; (3) the design of a GaAs RAM cell capable of very low static power dissipation (>1 µW/bit).

A novel low-power static GaAs MESFET logic gate

A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved.

Oxide-isolated integrated Schottky logic

Integrated Schottky logic has been fabricated in an oxide-isolated technology using 5 /spl mu/m lines and spaces. The novel device uses a merged substrate p-n-p (base width /spl sime/1.0 /spl mu/m) to clamp the collector-base junction of the oxide-walled base, down-operated n-p-n transistor. Ion-implanted low-barrier PtSi-nSi Schottky diodes are used for n-p-n collector decoupling. The average propagation delay measured on a 25-stage ring oscillator (fan-in=fan-out=1) was 2.3 ns at 65 /spl mu/A/stage and 25/spl deg/C. This 150 fJ/V power-delay product is a 3.6/spl times/ improvement compared with 540 fJ/V for junction-isolated ISL (2.7 ns at 200 /spl mu/A/stage).

A 1-µm bipolar VLSI technology

A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L and STL device designs. Power-delay products of 14 fJ for I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L and 30 fJ for STL have been measured.

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.

Design and performance of GaAs normally-off MESFET integrated circuits

DC and transient analyses of GaAs normally-off MESFET integrated circuits are described. The design tradeoffs between device parameters and logic characteristics are discussed for an inverter with a resistive load. By increasing the supply voltage to several times that of the built-in voltage, the propagation delay time can be lowered similar to that when using an active load (current source). To investigate the speed-power performance of the IC's, ring oscillators with different fan-in and fan-out configurations were fabricated. A binary frequency divider which uses a master-slave flip-flop was tested. The maximum counting frequency of the divider was 610 MHz at a supply voltage of 1.5 V. This coincides with the results obtained from the ring oscillators with fan-in/fan-out = 2/2. Comparing the experimental results with the theory, the effective electron mobility in the thin channel layer is expected to be very low. By improving the mobility and shortening the gate length to half a micrometer, practical functioning circuits should operate with an average propagation delay time of less than 100 ps.

A 3000-Gate CMOS Masterslice LSI

A new CMOS masterslice LSI has been developed. This LSI adopts silicon gate CMOS of 3.6 µm gate length and double layer metal interconnection process. It can take up to 3000 effective gates without any special cooling requirement. The average propagation delay time is 7 ns/gate and the power dissipation of an LSI is 50 mW at 10 MHz operation. By suitable DA support, it becomes possible to develop LSI's in quick turnaround time avoiding design changes or errors.

A new high-voltage analog-compatible I/sup 2/L process

A new technique for realizing high-performance I/SUP 2/L circuits simultaneously with high-voltage analog circuits is described. The method is flexible and may be used with any standard linear bipolar process. Only one additional noncritical masking step and one phosphorus implant are required to form the I/SUP 2/L n-wells. Experimental results are presented which show I/SUP 2/L betas of greater than eight per collector with the I/SUP 2/L BV/SUB CEO/ exceeding 3 V. The measured minimum average propagation delay is 40 ns using a 14 /spl mu/m thick, 5 /spl Omega/.cm epitaxial layer, while the analog BV/SUB CEO/ exceeds 50 V.

Fabrication of integrated injection logic with electron-beam lithography and ion implantation

Integrated injection logic gates have been fabricated using electron-beam lithography and ion implantation. A factor of five reduction in gate area over conventional designs was achieved by using minimum linewidths of 1.25 µm. Average propagation delay of 6 ns at 100 µA/gate injector current and speed-power product of 0.13 pJ at 5 µA have been measured on five collector, stick geometry, n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> guard ring device structures. The delay time is a factor of three and the speed-power product is a factor of five better than typical conventionally sized structures fabricated with photolithography. A minimum delay of 3.6 ns has been achieved on five collector device structures designed for maximum speed.

A Subnanosecond Masterslice LSI Using Dielectric Isolation and Three Layer Metallization Technologies

A high speed bipolar masterslice LSI has been realized which contains 400 internal gate cells and 60 output gate cells on a 5.7 mm × 5.7 mm chip. Oxide isolation with n-type epiataxial layer and three layer metallization by PMP structure are used for fabrication process. These new technologies afford a large reduction in device size, parasitic capacitance and wiring area, which improve LSI performance. An internal gate is realized by the CML circuit with a 400 mV logic swing and with emitter followers, together with extensive use of emitter-dotting and collector-dotting. Power supply voltage is -3.2 V and output level is compatible with standard ECL. The ALU chip has been fabricated for an application of this masterslice LSI and a 1.48 ns average propagation delay per circuit has been achieved.