A 1-µm bipolar VLSI technology

S.A Evans,L.A Arledge,C.R Fuller,J.O Englade,S.A Morris

doi:10.1109/t-ed.1980.20042

S.A Evans, L.A Arledge + Show 3 more

https://doi.org/10.1109/t-ed.1980.20042

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A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I 2 L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I 2 L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I 2 L and STL device designs. Power-delay products of 14 fJ for I 2 L and 30 fJ for STL have been measured.

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