A Subnanosecond Masterslice LSI Using Dielectric Isolation and Three Layer Metallization Technologies

Abstract

A high speed bipolar masterslice LSI has been realized which contains 400 internal gate cells and 60 output gate cells on a 5.7 mm × 5.7 mm chip. Oxide isolation with n-type epiataxial layer and three layer metallization by PMP structure are used for fabrication process. These new technologies afford a large reduction in device size, parasitic capacitance and wiring area, which improve LSI performance. An internal gate is realized by the CML circuit with a 400 mV logic swing and with emitter followers, together with extensive use of emitter-dotting and collector-dotting. Power supply voltage is -3.2 V and output level is compatible with standard ECL. The ALU chip has been fabricated for an application of this masterslice LSI and a 1.48 ns average propagation delay per circuit has been achieved.