Arithmetic Unit Research Articles

Physically unclonable functions based on small delay defects in QCA

Physically unclonable functions (PUFs) as a physical security entity are widely used in conventional CMOS technology. The specific structure of circuits in quantum dot cellular automata (QCA) technology does not allow the use of the same techniques of CMOS to effectively applied for implementation of PUF in QCA. However, the QCA technology is much susceptible to various random fabrication defects. A large group of these defects is small delay defects (SDDs) that cannot cause a fault at the nominal conditions. In this paper, we propose a PUF construction based on SDDs as a physical feature of QCA technology. For simulation, we randomly inject defects in a circuit, particularly the majority voter gates in an arithmetic unit. A set of picked challenges is applied to the circuit to excite SDDs. The existence of SDDs is disclosed using a new delay-based model that also converts the size of defect to a bit string. Finally a collection of bit strings corresponding to the size of SDDs forms the PUF response or the signature of the entity. The results of simulations exhibit the benefit of SDDs for the realization of PUF in QCA. The extracted signatures satisfy the required robustness and security measures for the PUF objectives such as identification.

A formal model for proving hardware timing properties and identifying timing channels

Timing channels are becoming a critical threat to hardware security. When exploited, secret information can be revealed by analyzing the execution time statistically. There are a variety of methods for detecting timing channels such as statistical analysis, testing and formal verification. However, existing methods cannot guarantee that the timing channels can be identified due to limited test coverage or high performance overhead. In this work, we introduce a novel model for evaluating timing variations of the hardware design. Furthermore, we propose a systematical solution that integrates time label enhanced tracking logic and formally verifies the timing invariant property of hardware designs in order to identify hardware timing channels. We demonstrate our solution on several hardware implementations, including arithmetic units, cryptographic cores and cache. The proof results show that our solution can detect hardware timing channels effectively.

Analysis of effectiveness of power on refined numerical models of floating point arithmetic unit for biomedical applications

“The technology defined today might be redefined tomorrow”- from the quotes, in the modern era redefining the architecture with the optimization of area, delay and reduction of power is focused more than fixed models. This paper describes the floating point arithmetic unit and insists the importance of it, in real time signal processing. The present trends of portable devices for medical applications need occupancy of smaller area with long span time life of battery. The bio medical signals are converted into IEEE 754 format as BIF. Hence it is easily analyzed in FPGAR devices and also this work insists the importance of redefining the architecture with reduction of critical path delay. The FPU arithmetic unit has the blocks to perform the computations like addition, Multiplication and division operation. The main architecture is constructed using top level design with individual blocks defined as a part of it. The floating point unit defined with modern FPGAR (Reconfigurable FPGA) increase the speed of computation and enables the flexibility and adopted to the hardware reconfigurable models. A 32 bit representation of IEEE 754 results of FPU is stored in the data storage and this process optimize the critical path between blocks. The way its programmed consumes lower level of power consumption in the range of 50.4 nw and delay of 25.2 ns and also modern adder structure with 6T type was used to implement the intermediate blocks of multiplier in FPU block as part of computing partial products. By this process of FPU redefining, reduce the number of slice to 206 and increase the operating frequency of 46.12 MHz.

Novel high functionality fault tolerant ALU

Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.

An ultrafast all-optical half adder using nonlinear ring resonators in photonic crystal microstructure

Half adder and half subtractor are the basic building blocks of an arithmetic logic unit used in every optical central processing unit (CPU) to provide computational operators. In this paper, we aim to design an ultrafast all-optical half adder based on nonlinear ring resonators. The proposed structure consists of the concurrent designs of the AND and XOR logic gates inside a rod-based photonic crystal microstructure. The linear dielectric rods made of silicon and nonlinear dielectric rods composed of doped glass are used to design the nonlinear ring resonators as the fundamental blocks of a half adder. We demonstrate as the intensity of the incoming light increases, the nonlinear Kerr effect appears, and the total refractive index increases. It diverts the direction of light propagation to the desired nonlinear ring resonator depending on the signal wavelength, the radius of rods and lattice constant. Finally, after several resonances, the light is coupled to the output. Our numerical simulations using a two-dimensional finite-difference time-domain method reveal depending on the light intensity, the maximum and minimum transmissions of the half adder are 100% and 96%, respectively. The calculations also show the delay of the designed half adder is 3.6 ps. Due to the small area of 249.75 µm2, the proposed half adder is an appropriate candidate for photonic integrated circuits used in the next generation of all-optical CPUs.

Effective CU Design Based Implementation of a 64-Bit Processor for Signal Processing Applications

The aim of this paper is to design simple and Effective digital control unit for a 64-bit processor core. Proposed idea is implemented in Spartan-III FPGA Architecture. Control unit (CU) directs the operation of the processor to get results. The function of CU is to fetch their instructions, examining them and execute the programs stored in the memory and executing them one after another in Main Memory. The Central Processing Unit (CPU) is the combination of Arithmetic and Logic Unit (ALU) and CU. The CPU receives information from several different elements; they are memory, control path and data path. Control Unit is required to produce the control signals for operating data path at each clock cycle. CU generates instructions to the memory, arithmetic/logic unit and input and output devices. The proposed control unit simulated in Xilinx and implemented in Spartan 3E , achieved less delay compared to existing approaches

A power and area efficient approximate carry skip adder for error resilient applications

The compute-intensive multimedia applications on portable devices require power and area efficient arithmetic units. The adder is a prime building block of these arithmetic units and limits the overall performance. Therefore, this paper analyzes the logic operations of the state-of-the-art adders and presents a novel low complexity adder segment with new carry prediction logic by removing the redundant logic and sharing the common operations. Further, a new power and area efficient approximate carry skip (PAEA-CSK) adder is proposed using the novel adder segment. The effectiveness of the proposed PAEA-CSK adder is evaluated and compared over the existing adders by implementing them in VHDL and synthesizing using the Synopsys Design Compiler with the 65nm TSMC CMOS Library. The synthesis result shows that the proposed PAEA-CSK adder requires $27.28\%$ and $18.03\%$ less area and power, respectively, over the existing carry skip-based approximate adder with the same accuracy. Further, the Sobel edge detector (SED) embedded with the proposed adder improves PSNR by a minimum of 16.94 dB over the SED embedded with a nonzeroing bit-truncation adder.

Low power and area efficient error tolerant adder for image processing application

SummaryApproximate computing‐based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1‐bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16‐bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal‐to‐noise ratio (PSNR).

An efficient fault-tolerant arithmetic logic unit using a novel fault-tolerant 5-input majority gate in quantum-dot cellular automata

This paper proposes a novel fault-tolerant 5-input majority gate using 28 simple and rotated cells in Quantum-dot Cellular Automata (QCA) technology. The proposed gate is evaluated against cell omission, extra-cell deposition, and cell displacement defects to check the stability. The simulation results using QCADesigner 2.0.3 software show that the proposed gate is 59% and 100% fault-tolerant against single-cell omission and extra-cell deposition defects, respectively. It also shows good tolerance against cell displacement defects. Moreover, the functionality of the proposed structure is confirmed by physical proofs. QCAPro tool is used to analyze the power consumption of the proposed structure. Fault-tolerant versions of basic gates including 2-input AND, 2-input XOR, and 3-input XOR are suggested using the proposed gate. Moreover, a fault-tolerant 2:1 multiplexer, a 4-bit even parity generator, and an Arithmetic Logic Unit (ALU) are developed and implemented using the proposed fault-tolerant basic gates.

An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic

High computational complexity of multimedia applications on the portable devices demands a high speed and energy efficient processing cores. The performance of arithmetic unit within these cores significantly affects the overall performance of the devices. Therefore, this paper presents carry look ahead (CLA) adder based two efficient accuracy reconfigurable (AR) adder designs namely AR-CLA-I and AR-CLA-II. The AR-CLA-I design is developed using 4-bit CLA segments with novel approximate sum generation approach. Whereas, the AR-CLA-II design is developed using a novel complementary logic based CLA segment which utilizes proposed new logic formulation. The proposed AR-CLA designs can be reconfigured to achieve high energy-efficiency at cost of acceptable loss in quality. The synthesis results on TSMC 65nm CMOS technology library show that the proposed AR-CLA-I (AR-CLA-II) provides on average 76.52% (80.62%) and 71.65% (74.16%) less area and energy respectively over the best available CLA based approximate adder. The quality metrics of the proposed AR-CLA adder designs as standalone unit demonstrates significant improvement over the existing approximate adder designs. Finally, Sobel edge detectors (SED) embedded with proposed AR-CLA adders provide 71.89 dB higher PSNR over SED embedded with best known approximate adder.

Design and Performance Investigations with Ultra High Speed Optical ALU

Abstract All-optical arithmetic and logic unit is an integral part of contemporary optical data processing network. Accordingly, in this paper a method to develop all-optical arithmetic unit has been proposed. The proposed logic unit consists of semiconductor optical amplifier (SOA) whose fast non-linear characteristics have been utilized for the execution of numerous binary logic operations such as AND, OR, NAND, NOR, EXOR, buffer etc., as well as arithmetic operations, for instance half-addition and half-subtraction, etc. Numerical simulations for the various logic operations have been realized and output verified for the 100 Gbps data rate. Numerical executions have been also done for the crucial key parameters as the bias voltage, confinement factor, and laser power, yielded with good extinction ratio more than 10 dB. The proposed design consists of SOA with benefits of design as rapid switching speed, consumes low power and avoids optoelectronic translation. The design is having with good prospect for impending all optical complex computing networks.

A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. We have proposed a novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation, delay and device count. Further, the P-MALU circuit is extended for 4-bits arithmetic operations. Electrical simulations are performed to verify the functionality of the design for higher bit operations which demonstrates the feasibility of the proposed design in VLSI circuits.

Design and Analysis of an Arithmetic and Logic Unit using Single Electron Transistor

The demand for low power dissipation and increasing speed elicits numerous research efforts in the field of nano CMOS technology. The Arithmetic Logic Unit is the core of any central processing unit. In this paper, we designed a 4-bit Arithmetic and Logic Unit (ALU) using Single Electron Transistor (SET). Single-electron transistor (SET) is a new type of switching nanodevice that uses controlled single-electron tunneling to amplify the current. The single-electron transistor (SET) is highly scalable and possesses ultra-low power consumption when compared to conventional semiconductor devices. Reversible logic gates designed using SET are used for performing 4-bit arithmetic operations. We modelled symmetric single gate SET operating at room temperature using Verilog A code. The design is carried out in cadence simulation environment. The 4-bit SET based ALU design exhibits the power of 0.52 nW and delay of 350pS.

A High-Performance Design of Generalized Pipeline Cellular Array

In this letter, we proposed a high-performance quantum-dot cellular automata (QCA) design of generalized pipeline cellular array (GPCA). The GPCA can perform all the basic arithmetic operations using only one arithmetic cell. Due to its flexibility, the high-performance GPCA design is of high interest for large-scale QCA designs. We proposed both the arithmetic unit and control unit designs of GPCA using a hybrid logic network that represented by majority-of-three (MAJ), inverter (NOT), and three-input exclusive-OR (XOR 3 ). The introduction of XOR 3 operation can significantly reduce the number of gates, levels, and wire-crossings, which in turn results in less area and fewer clock cycles of QCA layout. Experiments show that we can achieve both area and latency improvements of n-bit (n = 3,4,5) GPCA designs compared with the-state-of-art.

Controlled hardware architecture for fractal image compression

Fractal image compression utilising algorithms have a high demand on the memory interface and the processor's arithmetic unit, which in turn fails to utilise the full capabilities of a general purpose processor. Since the algorithm is repetitive, the parallelisation reduces the time complexity of the otherwise expensive coding scheme. The design for FIC is proposed in this paper. It is based on the fact that the algorithm requires only integer arithmetic with repetitive use of the same data set. Making use of multiple functional units, controlled parallelism is introduced in this process. This makes encoding time 80 times faster than high level software implementation. It is 25 times faster than the assembly level implementation on a DSP processor.

Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach

In view of the problems arising due to the scaling of the silicon transistor, different post-silicon, post-binary logic technologies are being explored by researchers. Implementation of Ternary Logic Circuits using Carbon Nanotube Field Effect Transistors (CNTFETs) is one such alternative. CNTFETs are an ideal choice for implementing ternary logic circuits since using CNTFETs multiple threshold voltages can be obtained by changing their physical dimensions. This paper presents a new design for a 2-digit Ternary Arithmetic and Logic Unit (TALU) using CNTFETs. The proposed TALU architecture consists of a function select block, a transmission gate block, and functional modules. In this design, the functional modules are implemented using a 2:1 multiplexer based design approach. This eliminates the need for decoders at the input resulting in lesser number of transistors when compared to existing designs. The proposed 2:1 multiplexer based approach results in lower power consumption in proposed Adder-subtractor and Multiplier modules as compared to existing ones. HSPICE based circuit simulations were performed on the proposed and existing TALU designs. Simulation results show an improvement of up to 96% in power and up to 95% in PDP for the Adder-subtractor and Multiplier modules. An improvement of up to 90% in power and up to 93% in PDP is obtained for the proposed TALU design as compared to the designs existing in the literature.

Parallel implementation for ECCP based on Montgomery ladder algorithm

An Elliptic Curve Crypto-Processor (ECCP) is a favourite public-key cryptosystem. It is used for embedded systems due to its small key size and its high security arithmetic unit. It is applied in constrained devices which often run on batteries and have limited processing, storage capabilities and low power. A finite field polynomial multiplier takes the most implementation effort of an ECCP because it is the most consuming operation for time and area. So, it is preferable to optimize this operation especially for light devices where the small area is needed. This research introduces a hardware design for parallel ECCP binary implementation that is based on Montgomery ladder algorithm. This implementation is targeted for GF(2163) and GF(2409) where the executed time are 2.9 μs and 29 μs respectively. The implementation is performed on Xilinx ISE Virtex6.

Clock Delayed Dual Keeper Domino Logic Design with Reduced Switching

Clock Delayed Dual Keeper domino logic style with Static Switching mechanism (CDDK_SS) using delayed enabling of the keeper circuit and modified discharge path has been proposed in this paper. In CDDK domino circuit, the principle of delayed enabling of keeper circuit offers reduced contention between keeper circuit and Pull Down Network (PDN). The modified discharge path at the output node eradicates the switching at the output node for identical TRUE inputs during the pre-charge phase. This facilitates in obtaining static like output in contrast with conventional domino logic. The simulation results of Arithmetic and Logic Unit (ALU) subsystems demonstrate 17.7% reduction in dynamic power consumption while compared to conventional domino logic. Furthermore, 62% enhancement in speed performance has been achieved with good robustness. Design and simulation have been executed using Cadence® Virtuoso, with UMC 90nm technology node library.

A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process

The Block Decoder (BD) which is an indispensable component of the JPEG 2000 image compression standard has the highest computational complexity and determines the speed of the overall decoder system. This paper proposes a high throughput pass parallel BD architecture, which can decode more than one bit per clock cycle. In BD, the dependency between context generation and arithmetic decoding unit incorporates stalling and reduces the throughput of the decoding process. The proposed selective byte input and synchronous sample skipping techniques are used to prevent stalling in the decoding process. The proposed architecture achieves 86% more throughput with 50% increment in the hardware cost than that of the best available serial BD architecture. In comparison with the best available pass parallel architecture, throughput improves almost 8.2 times with 61% increment in the hardware cost. Incorporation of the speed up techniques in the design is the main reason for more hardware consumption. The Figure of Merit of the proposed design, which is the ratio of throughput and hardware cost, is more than that of the available BD architectures for typical code block (CB) size of 32 × 32. The ASIC implementation of the proposed design consumes 66 mW power at maximum operating frequency.

Transición de la aritmética al álgebra: Un estudio con estudiantes universitarios de Nicaragua

&#x0D; &#x0D; &#x0D; El siguiente artículo presenta los resultados de una investigación sobre las principales dificultades que afectan la transición de la aritmética al álgebra en los estudiantes de la Universidad Nacional Autónoma de Nicaragua, Managua (UNAN-MANAGUA), específicamente en la Facultad Regional Multidisciplinaria de Chontales (FAREM-Chontales). Es un tema de actualidad permanente en la Didáctica de la Matemática. En la revisión de la literatura se encontraron algunos conceptos importantes que permiten mejorar estas dificultades. El tipo de muestreo utilizado fue el no probabilístico, por tratarse de un estudio de enfoque mixto, el mismo se definió de forma voluntaria, tomando como criterio la forma que los estudiantes respondían el test, opinando y expresando sus ideas en la entrevista. Se analizaron los aspectos importantes sobre cómo mejorar las dificultades presentadas en el desarrollo de los contenidos de las unidades de aritmética y álgebra. Se concluye que el conocimiento que los estudiantes adquieren en el desarrollo de los contenidos de la unidad de aritmética y de álgebra es fundamental para las asignaturas siguientes al igual que en su ámbito profesional.&#x0D; &#x0D; &#x0D;