Controlled hardware architecture for fractal image compression

Abstract

Fractal image compression utilising algorithms have a high demand on the memory interface and the processor's arithmetic unit, which in turn fails to utilise the full capabilities of a general purpose processor. Since the algorithm is repetitive, the parallelisation reduces the time complexity of the otherwise expensive coding scheme. The design for FIC is proposed in this paper. It is based on the fact that the algorithm requires only integer arithmetic with repetitive use of the same data set. Making use of multiple functional units, controlled parallelism is introduced in this process. This makes encoding time 80 times faster than high level software implementation. It is 25 times faster than the assembly level implementation on a DSP processor.