Arithmetic Unit Research Articles

Four Arithmetic Operations on the Quantum Computer

Quantum computer has been proved to be superior to electronic computer in solving some NP problems. Based on the former quantum adder, this paper proposes a new quantum adder and quantum subtracter, and then designs a fixed-point quantum multiplier and a fixed-point quantum divider based on fixed-point number operations. Four arithmetic units are presented using quantum gate circuits. These researches lay a foundation for the quantum implementation of digital filters.

Design of a Four-stage Pipelined Reduced Instruction Set Computing Microprocessor

This work presents the design of a reduced instruction set computing (RISC) microprocessor in a four-stage pipeline architecture. The nuts and bolts of each block including timing diagrams are elaborated. To be more specific, a hardware solution to pipeline hazards is proposed and verified, i.e. provided the current result of the arithmetic logic unit (ALU) is employed by the next instruction, the FOWARDING_EN goes high and commands the ALU to select the forwarded result as the updated input, rather than the stale value read from the random-access memory (RAM), thus obviating the need to wait for another two cycles until the expected data has been written back. For the design with data forwarding, two limitations were discovered and tackled successfully by a software solution. Active-HDL was employed to verify the design by simulating a case study, with the code presented in the Appendix.

Montgomery Multiplication for Public Key Cryptography on MSP430X

For traditional public key cryptography and post-quantum cryptography, such as elliptic curve cryptography and supersingular isogeny key encapsulation, modular multiplication is the most performance-critical operation among basic arithmetic of these cryptographic schemes. For this reason, the execution timing of such cryptographic schemes, which may highly determine that the service availability for low-end microprocessors (e.g., 8-bit AVR, 16-bit MSP430X, and 32-bit ARM Cortex-M), mainly relies on the efficiency of modular multiplication on target embedded processors. In this article, we present new optimal modular multiplication techniques based on the interleaved Montgomery multiplication on 16-bit MSP430X microprocessors, where the multiplication part is performed in a hardware multiplier and the reduction part is performed in a basic arithmetic logic unit (ALU) with the optimal modular multiplication routine, respectively. This two-step approach is effective for the special modulus of NIST curves, SM2 curves, and supersingular isogeny key encapsulation. We further optimized the Montgomery reduction by using techniques for “Montgomery-friendly” prime. This technique significantly reduces the number of partial products. To demonstrate the superiority of the proposed implementation of Montgomery multiplication, we applied the proposed method to the NIST P-256 curve, of which the implementation improves the previous modular multiplication operation by 23.6% on 16-bit MSP430X microprocessors and to the SM2 curve as well (first implementation on 16-bit MSP430X microcontrollers). Moreover, secure countermeasures against timing attack and simple power analysis are also applied to the scalar multiplication of NIST P-256 and SM2 curves, which achieve the 8,582,338 clock cycles (0.53 seconds@16 MHz) and 10,027,086 clock cycles (0.62 seconds@16 MHz), respectively. The proposed Montgomery multiplication is a generic method that can be applied to other cryptographic schemes and microprocessors with minor modifications.

LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing

Several applications such as signal processing, multimedia and big data analysis exhibit computational error tolerance. This tolerance can be exploited to achieve efficient designs by sacrificing accuracy. Therefore, approximate computing presents a new design paradigm that smashes the traditional belief of error-free computations and provides efficient design with quality metrics specific to an application. The multiplication operation significantly determines the performance of the core due to the compute intensive operation. Therefore, this paper proposes a novel leading one bit based approximate (LoBA) multiplier architecture that selects k-bits from n-bit inputs (k ≤ n/4) based on leading one bit (LOB) and then computes approximate product based of these small input. The accuracy is further improved by selecting next k-bits based on LOB position and considering the partial product for computing final product. Four imprecise LoBA multipliers are presented that provide trade-off between accuracy and performance. Finally, the effectiveness of the proposed architectures is shown over the existing multipliers as standalone arithmetic unit and in the application by implementing Gaussian smoothing filters. The proposed 16-bit LoBA0 and LoBA1 designs reduce power consumption by 64.2% and 32.9%, respectively over the existing multiplier architecture.

FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

Electronic-photonic arithmetic logic unit for high-speed computing

The past two decades have witnessed the stagnation of the clock speed of microprocessors followed by the recent faltering of Moore’s law as nanofabrication technology approaches its unavoidable physical limit. Vigorous efforts from various research areas have been made to develop power-efficient and ultrafast computing machines in this post-Moore’s law era. With its unique capacity to integrate complex electro-optic circuits on a single chip, integrated photonics has revolutionized the interconnects and has shown its striking potential in optical computing. Here, we propose an electronic-photonic computing architecture for a wavelength division multiplexing-based electronic-photonic arithmetic logic unit, which disentangles the exponential relationship between power and clock rate, leading to an enhancement in computation speed and power efficiency as compared to the state-of-the-art transistors-based circuits. We experimentally demonstrate its practicality by implementing a 4-bit arithmetic logic unit consisting of 8 high-speed microdisk modulators and operating at 20 GHz. This approach paves the way to future power-saving and high-speed electronic-photonic computing circuits.

A Memristive Multiplier Using Semi-Serial IMPLY-Based Adder

Memristors are among emerging technologies with many promising features, which makes them suitable not only for storage purposes but also for computations. In this work, focusing on in-memory computations, we first present our semi-serial IMPLY-based adder and perform an extensive analysis of its merits. In addition to providing a favorable balance between the number of steps and number of memristors, a key property of the presented adder is its compactness as compared to the state-ofthe-art adders. Next, using our semi-serial adder, we propose an IMPLY-based multiplier. We show that the proposed multiplier is more than 5× better than other works based on the figure of merit which gives equal weight to the number of steps (i.e., speed) and required die area. Additionally, we provide a deeper insight into IMPLY-based arithmetic units, their properties, design characteristics, and advantages or disadvantages compared to one another by proposing new figures of merit and performing comprehensive comparative analyses. This facilitates the process of design, or selection, of suitable units for the design engineers and researchers in the field.

Realization of Various Topologies of Adders Based on H-Dycml

Power consumption minimization in a circuit becomes imperative with growth in demands of portable goods. However, at the same time, its speed limits the performance of a system. Therefore, there is a need of choosing optimum circuit architecture that takes into account the both conflicting parameters, that is, power dissipation and speed. Arithmetic unit is one of the vital components of portable goods and out of all arithmetic operations, adders are the most commonly used. To address the issue of high power dissipation, low-power designing styles are becoming prominent now-a-days. Hybrid Dynamic Current Mode Logic is high-speed, low-power designing style that has been recently proposed in literature. Therefore, this paper presents the comparison between performances of various topologies of adders that are implemented using a high-speed, low-power designing style: Hybrid-Dynamic Current Mode Logic (H-DyCML). All the circuits are realized in Cadence Virtuoso using 180nm CMOS technology parameter. Various performance parameters are evaluated such as: Delay, Power, Power-Delay Product, and hardware utilization. It is found that carry look-ahead adder out-stands other adders in terms of overall performance.

A semi-custom design methodology and environment for implementing superconductor adiabatic quantum-flux-parametron microprocessors

We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm−2 Nb high-speed standard process as well as the AIST 2.5 kA cm−2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14–37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.

Urdhva Tiryak Sutra Based Ancient Multiplication in Reversible Logic Circuits

The proposed work analyses the employment of an ancient mathematical approach for building an arithmetic logic unit. Dissipation of power is one of the major driving issues in VLSI design. With the assistance of reversible gates, the power dissipation and loss of information can be minimized. The speed and accuracy of the Arithmetic Logic Unit depends on the propagator. Employing the traditional mathematics sutras technique within the computation algorithm reduces the complexity, duration and power. Due to the effect of environmental factors on the digital circuits, parity conserving technique is incorporated for providing error detection ability. The proposed work deal with the design and analysis of 32 bit reversible multiplier using ancient sutras with and without parity conserving technique .The planned work is implemented on Xilinx ISE Spartan 6E series of FPGA and simulation results are obtained. By using Cadence EDA tool, power, area and delay are calculated. The quantum parameters are calculated manually for 32-bit reversible multiplier using ancient technique with and without parity conserving technique using Urdhva Tiryakbhyam sutra.

LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC

The full adder is a key element of any arithmetic logic units used in microprocessor systems. For microprocessor components created for modern mobile digital devices, compact layout design on the silicone chip is of great importance. In this paper an area effective layout design on the chip is proposed for 4-bit ripple carry adder based on pass transistor logic. The full adder is simulated using EDA tool and output signal waveforms are obtained to demonstrate the functionality of the design. It is shown that 1-bit full adder based on pass transistor logic and composed of two 3T XOR gates and one 2T multiplexer allows us to obtain area effective layout design on the chip for 4-bit ripple carry adder providing acceptable characteristics for output signals.

Probing the operability regime of an engineered ribocomputing unit in terms of dynamic range maintenance with extracellular changes and time

Synthetic biology aims at engineering gene regulatory circuits to end with cells (re)programmed on purpose to implement novel functions or discover natural behaviors. However, one overlooked question is whether the resulting circuits perform as intended in variety of environments or with time. Here, we considered a recently engineered genetic system that allows programming the cell to work as a minimal computer (arithmetic logic unit) in order to analyze its operability regime. This system involves transcriptional and post-transcriptional regulations. In particular, we studied the analog behavior of the system, the effect of physicochemical changes in the environment, the impact on cell growth rate of the heterologous expression, and the ability to maintain the arithmetic functioning over time. Conclusively, our results suggest 1) that there are wide input concentration ranges that the system can correctly process, the resulting outputs being predictable with a simple mathematical model, 2) that the engineered circuitry is quite sensitive to temperature effects, 3) that the expression of heterologous small RNAs is costly for the cell, not only of heterologous proteins, and 4) that a proper genetic reorganization of the system to reduce the amount of heterologous DNA in the cell can improve its evolutionary stability.

The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate

Inverter and majority gates are considered as two important primitive gates for designing logical circuits in the quantum-dot cellular automata (QCA) technology. Up to now, many QCA layouts have been introduced for three-input majority gates, most of which are not robust against the QCA defects and so they are prone to faults. In this paper, we propose an efficient fault-tolerant 3-input majority gate with ten simple and rotated cells whose output signal strength is very high (± 9.93e−001). The fault tolerance of the proposed structure is investigated against cell omission, extra-cell deposition, and displacement defects. The results show that the proposed structure is 100% and 90% tolerant against single-cell omission and extra-cell deposition defects. Moreover, the error probability of the proposed gate under cell omission and extra-cell deposition defects is investigated through analytical modeling. Using the proposed fault-tolerant structure, two basic circuits including a fault-tolerant QCA full-adder and a fault-tolerant 2:1 QCA multiplexer are introduced. Finally, using the proposed circuits, a fault-tolerant one-bit arithmetic logic unit with four mathematical and logical operations is designed and implemented. To verify the proposed three-input majority gate, some physical proofs are provided. The results of simulations by QCADesigner 2.0.3 show that the proposed circuits work well. The power analysis of the proposed structure is performed using a QCAPro tool. The comparison results show that the proposed circuits are much better than the previous designs.

Optimized Gate Diffusion Input Method-Based Reversible Magnitude Arithmetic Unit Using Non-dominated Sorting Genetic Algorithm II

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers.

Complex exponential functions: A high-precision hardware realization

Hardware realization of complex exponential functions (CEF) is not practical for over 16-bit operands. This is due to high cost and delay of the required look-up table (LUT) and arithmetic units. Therefore, we decompose larger (up to 64 bits) operands to three parts (e.g., 11+24+29=64). They are handled by minimax approximation, one-dimensional degree-3 interpolation, and pure LUT approaches, respectively. However, the second one is not used for smaller operands. Taking advantage of rectangular multipliers, we have realized high precision CEF, on FPGA platform. More than 30% speedup and 75% lower cost are achieved in comparison with the previous relevant works.

A Dynamical Machine Control System using Simple Processing Unit Based-on FPGA

This paper aims to design a dynamic machine control system device. The proposed dynamic device models are a combination architecture of memory and Arithmetic-Logic Unit (ALU). The configuration of the memory has used a random access memory (RAM), and the configuration of ALU is the core of the central processing unit (CPU), which consists of two functions, namely the arithmetic unit and the logical unit. In this paper, the arithmetic unit consists of addition, subtraction, multiplication, and division, whereas the logical units are AND, OR, NOT, and XOR. The shifter circuit in this paper was also applied to complete the programming code instructions in a software approach. The arithmetic unit and logic unit selector path in the ALU configuration employed a multiplexer circuit. This paper used a top-down design technique by determining the components in implementation. By knowing the function and work of these components, it is much easier to combine the components employing the configuration code of the hardware description language, namely a Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The implementation of the VHDL code was configured into the Xilinx Spartan-3E Field Programmable Gate Array (FPGA) to determine the component consumption and the resulted delay time. The results obtained from the configuration of the ALU components consume 26 slices, 50 4-input look-up table (LUT), 17 input/output (I/O), and 17 Bonded IO, while the component delay time is 11,413 ns.

Towards the Integration of Reverse Converters into the RNS Channels

The conversion from a Residue Number System (RNS) to a weighted representation is a costly inter-modulo operation that introduces delay and area overhead to RNS processors, while also increasing power consumption. This paper proposes a new approach to decompose the reverse conversion into operations that can be processed by the arithmetic units already present in the RNS independent channels. This leads to a more effective reuse of the processor circuitry while enhancing parallelism. Experimental results show that, when the proposed techniques are applied to architectures based on ripple-carry adders for the traditional 3-moduli set, the delay is improved in average by 16 percent, the circuit area by 36 percent and the power consumption by 47 percent. When carry-lookahead adder topologies are considered, these improvements are in average of 45 percent for the circuit area and 58 percent for the power consumption while the delay is only slightly reduced. The proposed techniques are applied to a use case in digital filtering, showing an increase in throughput/area of up to 1.25 times, and average reductions in energy consumption of 15.6 percent. This work is a step forward to the usage of RNS in practice, since reverse conversion underpins other hard inter-modulo operations, like comparison, scaling and division.

Synthesis of fast-operating devices for digital signal processing based on the number­theoretic transforms

The selection of special-form moduli and their corresponding primitive roots have been proposed, which provide for a simplified structure of arithmetic devices using number-theoretic transforms. A method for determining moduli has been developed that ensures a minimum number of arithmetic operations when performing the modulo addition and multiplication operations. The structures of special-form modulo adders have been developed and modeled, which make it possible to perform the addition operation as quickly as possible. The modulo adders for the Fermat, Mersenne, and Golomb numbers have been synthesized and tested, which could be used in the arithmetic units of high-speed correlators and filters. Real-time correlation and convolution calculation become a rather time-consuming task in the case of long input sequences. To solve this task, it is advisable to apply the so-called fast algorithms. However, this requires the high-performance calculators of convolution and correlation, which often exceed the capabilities of modern computer equipment, Therefore, the proposed procedure for determining the modulus, as well as the designed structural circuits for special-form modulo adders, make it possible to accelerate the computation of correlations and convolutions using number-theoretic transforms. Since the operation of modulo multiplication is performed using the addition and shift operations, the complexity of calculating the number-theoretic transformations largely depends on the number of unities in the binary representation of the degrees of the primitive root. The operation of multiplication is typically reduced to the multiple addition of numbers, which is why the complexity and speed performance of arithmetic devices for numeric-theoretic transformations is determined by the characteristics of the modulo adders. The proposed method for designing computing moduli for the digital devices that calculate correlation and convolution, based on rapid theoretical-numerical transformations, provides the simplified hardware and software implementation of these structures, resulting in high-speed processing of signals and images

Design and Implementation of FPU for Optimised Speed

Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need the speedy execution of arithmetic operations. In the existing system, the FPM(Floating Point Multiplication) and FPA(Floating Point Addition) have more delay and fewer speed and fewer throughput. The demand for high speed and throughput intended to design the multiplier and adder blocks within the FPM (Floating point multiplication)and FPA(Floating Point Addition) in a format of single precision floating point and double-precision floating point operation is internally pipelined to achieve high throughput and these are supported by the IEEE 754 standard floating point representations. This is designed with the Verilog code using Xilinx ISE 14.5 software tool is employed to code and verify the ensuing waveforms of the designed code.

Formal Verification of Hardware Components in Critical Systems

Hardware components, such as memory and arithmetic units, are integral part of every computer-controlled system, for example, Unmanned Aerial Vehicles (UAVs). The fundamental requirement of these hardware components is that they must behave as desired; otherwise, the whole system built upon them may fail. To determine whether or not a component is behaving adequately, the desired behaviour of the component is often specified in the Boolean algebra. Boolean algebra is one of the most widely used mathematical tools to analyse hardware components represented at gate level using Boolean functions. To ensure reliable computer-controlled system design, simulation and testing methods are commonly used to detect faults; however, such methods do not ensure absence of faults. In critical systems’ design, such as UAVs, the simulation-based techniques are often augmented with mathematical tools and techniques to prove stronger properties, for example, absence of faults, in the early stages of the system design. In this paper, we define a lightweight mathematical framework in computer-based theorem prover Coq for describing and reasoning about Boolean algebra and hardware components (logic circuits) modelled as Boolean functions. To demonstrate the usefulness of the framework, we (1) define and prove the correctness of principle of duality mechanically using a computer tool and all basic theorems of Boolean algebra, (2) formally define the algebraic manipulation (step-by-step procedure of proving functional equivalence of functions) used in Boolean function simplification, and (3) verify functional correctness and reliability properties of two hardware components. The major advantage of using mechanical theorem provers is that the correctness of all definitions and proofs can be checked mechanically using the type checker and proof checker facilities of the proof assistant Coq.