Abstract
A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.
Highlights
In recent years, there has been a strengthening link between advancement in computational technologies and components of physical systems
Parity check matrix H of QC-Low-Density Parity-Check (LDPC) code can be presented in the form of an array of submatrices, where “X” corresponds to the all-zero submatrix and a numerical value s corresponds to a an identity matrix circularly shifted by s positions to the right
The environment consists of three key elements: computer (PC), microcontroller and FPGA system
Summary
There has been a strengthening link between advancement in computational technologies and components of physical systems. Parity check matrix H of QC-LDPC code can be presented in the form of an array of submatrices, where “X” corresponds to the all-zero submatrix and a numerical value s corresponds to a an identity matrix circularly shifted by s positions to the right (i.e., columns are cyclically shifted by the indicated number). N (m)—a set of column indexes in the parity check matrix H containing one in the m-th row, M(n)—a set of row indexes in the parity check matrix H containing one in the n-th column, Rmn —message from the m-th control vertex to the n-th bit vertex of Tanner graph, xn —decoded vector It is known [21] that significantly improved decoding performance can be obtained by adding a normalizing parameter to Equation (2).
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