LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC

Alexey Gnilenko

doi:10.34185/1562-9945-1-126-2020-05

Abstract

The full adder is a key element of any arithmetic logic units used in microprocessor systems. For microprocessor components created for modern mobile digital devices, compact layout design on the silicone chip is of great importance. In this paper an area effective layout design on the chip is proposed for 4-bit ripple carry adder based on pass transistor logic. The full adder is simulated using EDA tool and output signal waveforms are obtained to demonstrate the functionality of the design. It is shown that 1-bit full adder based on pass transistor logic and composed of two 3T XOR gates and one 2T multiplexer allows us to obtain area effective layout design on the chip for 4-bit ripple carry adder providing acceptable characteristics for output signals.

Highlights

Arithmetic operations are considered as most important data conversions in digital signal processing systems
High speed, small surface area on the silicon chip and high reliability become very important factors for combinational logic devices designed for very large scale integration (VLSI) circuits
For really area effective full adder, a compact layout design on the silicone chip is of great importance

Summary

Introduction

Arithmetic operations are considered as most important data conversions in digital signal processing systems. High speed, small surface area on the silicon chip and high reliability become very important factors for combinational logic devices designed for VLSI circuits. «Системні технології» 1 (126) 2020 «System technologies» Conventional CMOS full adder design is based on complementary PMOS pull-up transistor and NMOS pull-down transistor networks [1,2].

Results

Conclusion