Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology

Abstract

For the past two decades, complementary static CMOS logic has been the dominant digital logic style because of its robustness and efficient deployment in standard cell based design flows. Pass Transistor Logic (PTL) has attracted much attention in the '90s; however, there are hardly any investigations for PTL in advanced commercial technology nodes and its use in larger circuits. In this paper, we investigate adders and multipliers circuits using PTL and demonstrate its advantages over complementary static CMOS logic in an advanced commercial FinFET technology. Special focus is put on process, voltage, and temperature (PVT) variations that are considered as large disadvantages of PTL. For this purpose, we select three most promising PTL-based 1-bit Full Adders (FA) based on an in-depth comparison of 22 PTL FAs to a complementary static CMOS logic reference using a recent 12nm FinFET technology. Layouts that are compatible with commercial standard cell libraries are implemented, hence all our results include extracted parasitics. We explore replacement strategies of standard adders by PTL adders in larger building blocks. In our designs, the PTL cells are interleaved with CMOS cells to reduce the circuit PVT sensitivity. Our investigation shows that PTL-based 1-bit adders achieve delay, average dynamic power, and Power-Delay-Product (PDP) reductions of up to 72.9%, 45.7%, and 78.5%, respectively, compared to the complementary CMOS logic based adder. Further, we demonstrate that our replacement strategy yields a PDP reduction of 39.6% for a 32-bit ripple-carry-adder, 22.6% for the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6\times 6$</tex> Baugh-Wooley multiplier, and 21% for an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> multiplier optimized by a state-of-the-art design flow.