Abstract
Full Adder (FA) is the very crucial cell of modern electronic processor and its arithmetic logical operations. To design the FA Circuits, the power and delay parameter are most significant consideration. The efficient FA is configured by complementary pass transistor logic, CMOS and transmission gate, etc. As technology goes smaller the Drain Induced Barrier Lowering (DIBL) is becoming a critical factor to design FA circuit. To overcome these issues, FinFET is projected to control on subthreshold conduction and leakage current. The FinFET is a multi-Gate device and can avoid the DIBL problems. In this paper, implemented the different types of high performance Full Adder with FinFET technology. Jyoti Kandpal, Hamed Naseri, Yavar Safaei Mehrabani and Mehedi Hasan projected circuits are implemented by using FinFET technology. All the operation of FA cell is conducted on 1.8 V and compares the performance based on driving capability and Power-delay product (PDP). Enhancing the quality and speed of electronic gadgets can be achieved by increasing the performance of full adder.
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