Complex exponential functions: A high-precision hardware realization

Abstract

Hardware realization of complex exponential functions (CEF) is not practical for over 16-bit operands. This is due to high cost and delay of the required look-up table (LUT) and arithmetic units. Therefore, we decompose larger (up to 64 bits) operands to three parts (e.g., 11+24+29=64). They are handled by minimax approximation, one-dimensional degree-3 interpolation, and pure LUT approaches, respectively. However, the second one is not used for smaller operands. Taking advantage of rectangular multipliers, we have realized high precision CEF, on FPGA platform. More than 30% speedup and 75% lower cost are achieved in comparison with the previous relevant works.