Antifuse Field Programmable Gate Array Research Articles

Measurements of radiation effects in an antifuse FPGA

This paper presents the irradiation and the measurement analysis for a commercial antifuse Field Programmable Gate Array (FPGA) from Microsemi’s Axcelerator family, part number AX250. Following proton and X-ray beam irradiation, at very high dose rate above 1krad/s, the total ionizing dose (TID) first effects were visible around 260 krad (SiO 2), and this threshold value increases at lower radiation dose rates. We expect for most space and accelerator applications that this value will be at least several Mrads, or even that the FPGA might never reach this threshold. At very high radiation dose rates, TID-induced leakage currents were observed in the device. FPGA data were recorded continuously for more than 100 h after each irradiation with a fully operating FPGA. Quantitatively, the room-temperature annealing of the radiation-induced defects leads to a fast decrease of the device leakage current by a factor of 7 in the first 100 h after irradiation. The last measurements done after three months place the currents to within 30% to 70 % relative to the before-irradiation values in case of two tested FPGA. Several firmware configurations were used to test different logic resources and to measure single event upsets (SEUs). An upper limit of SEU logic cross-section was found to be (2.56 ± 0.51) ⋅ 10−13 cm 2/FPGA for dose rates around 1krad/s. SEU cross-section values for RAM blocks have on average a value of (3.72 ± 0.8) ⋅ 10−14 cm 2/bit. The complete list of results is given and the effects are extrapolated to a high-energy physics experiment environment — LHCb RICH at CERN.

Design of Spaceborne Stepper Motor Driver Based on FPGA

In order to meet the specific application requirements of stepper motor in space optical remote sensor, such as large load current, low operating frequency, sufficient safety margin, anti radiation and other space environment indicators, a spaceborne stepper motor driver based on antifuse Field Programmable Gate Array (FPGA) is designed. The driver consists of power conversion module, control module, drive module, and position detection module. Using P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and N-channel MOSFET to design bipolar drive circuit, the driver hardware circuit is simple and the software resource occupancy rate is low. Through the experiments of the dual functions of logic protection circuit in hardware and dead zone protection in software, it is verified that the design of spaceborne stepper motor driver based on FPGA meets the requirements of space optical remote sensor mechanism control.

A study on the influence of dose rate on total ionizing dose effect of anti-fuse field programmable gate array—The irradiation damage is attenuated at low dose rate

The TID (total ionizing dose) in-situ experiments of LC1020B, an anti-fuse FPGA (Field Programmable Gate Array) device, were designed and carried out under different dose rates, and the influence of dose rate on the TID effect of FPGA was studied. The experimental results show that: 1) the TID irradiation failure of the FPGA under different dose rates has nothing to do with the input voltage parameter exceeding the standard. 2) with the decrease of cobalt source irradiation dose rate [171, 26.83, and 2.68 mGy(Si)/s], the TID effect failure dose threshold [168, 229, and 334 Gy(Si), respectively] of the FPGA gradually increased, showing obvious attenuation of low dose rate damage. Theoretical analysis suggests that, compared with the space charge limitation effect, the oxide charge annealing effect plays a dominant role, and longer irradiation time is beneficial to the oxide charge annealing. And based on the experimental data, an FPGA TID analytical model with power consumption current as the damage characterization parameter is established, which lays a foundation for scientific evaluation of radiation effect of anti-fuse FPGAs.

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs

There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory represents the majority of the memory elements in an FPGA. However, an FPGA-based platform could also be exploited to support the emulation of transient and permanent errors for designs intended to work in application-specific integrated circuits (ASICs) or radiation-hardened devices such as antifuse FPGAs. In this context, the obtention of a particular set of bits to flip is required to be able to emulate these error models. The main difficulty of this approach lies in determining the mentioned set of bits, which is due to the unavailability of a public description of the bitstream and the lack of FPGA architecture details. To help with this issue, we present a methodology to determine specific configuration memory bits from SRAM-based FPGAs that, when flipped, emulate permanent or transient upsets in any flip-flop element of the design under test. This methodology is proved in recent FPGA technologies and provides great control and precision in reliability experiments for harsh environments.

Silicon Carbide (SiC) Nanoelectromechanical Antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA Interconnects

We report a new nanoscale antifuse featuring low-power and high-programming speed, by employing silicon carbide (SiC) nanoelectromechanical systems (NEMS). We show that the SiC NEMS antifuses can enable ultralow-power one-time-programmable (OTP) field-programmable gate arrays (FPGAs) with characteristics promising for security-sensitive and harsh-environment applications. The SiC NEMS antifuses offer minimal leakage, low-programming voltage (down to $\sim 1.5$ V), ideally abrupt transient, high on/off ratios ( $>10^{7}$ ) and high-current carrying ability ( $>10^{6}$ A/cm $^{2}$ ), and very small footprints ( $\sim 1~\mu \text{m}^{2}$ to $\sim 0.1~\mu \text{m}^{2}$ per device). We further describe new designs of antifuses, simulate FPGA benchmarking circuits based on experimentally demonstrated practical NEMS antifuses, and compare their advantageous performance with state-of-the-art conventional antifuse FPGAs. We also demonstrate a SiC NEMS antifuse-based OTP memory cell with a read margin of $>10^{6}$ .

Long term storage reliability of antifuse field programmable gate arrays

Field Programmable Gate Arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve long operating life, there is a requirement to store un-programmed antifuse FPGA parts for long periods and program them when necessary to support the system. No study on the long term reliability of un-programmed antifuse FPGAs in the storage environment is reported in literature. In this paper, antifuse structures, programming process, and failure mechanisms of antifuse FPGAs are discussed. A failure modes, mechanisms and effects (FMMEA) analysis was performed for storage conditions and critical failure mechanisms were identified. High temperature storage tests of a select number of antifuse FPGAs were performed to accelerate the identified failure mechanisms. These parts were subsequently programmed and yield data was analyzed to determine the effects of high temperature storage.

Re-Programmable Antifuse FPGA Utilizing Resistive CeRAM Elements

A novel architecture utilizing resistive Correlated Electron Random Access Memory (CeRAM) elements to build re-programmable antifuse Field Programmable Gate Array (FPGA) components is introduced. Unlike traditional antifuse switching elements that can become permanently conducting upon application of the programming voltage, CeRAM antifuse elements can be subsequently switched back to an insulating state upon application of a reset voltage allowing the designer the freedom to re-configure the FPGA. Because the CeRAM element is based on a metal-insulator-metal (MIM) stack structure, it can be easily integrated in the upper metal layers of the fabrication process virtually eliminating the need for routing of channels between logic blocks. By utilizing CeRAM structures in the routing resources and as the block memory, it is possible to enhance the density by as much as 6 times, significantly reducing the size of the array while maintaining the use of existing low power logic styles.

Radiation Characterization of a Hardened 0.22 $\mu$m Anti-Fuse Field Programmable Gate Array

High energy particle measurements and analysis were performed on innovative Actel RTSX FPGA targets specifically designed, programmed, and operated representing realistic flight personalities. Results indicate these devices are suitable for space use following adequate application design and analysis

Radiation qualification of electronics components used for the ATLAS level-1 muon endcap trigger system

The ATLAS level-1 muon endcap trigger system is divided into three parts; one off-detector part and two on-detector parts. Application specific ICs (ASICs) and anti-fuse Field Programmable Gate Array (FPGAs) are actively used in the on-detector parts. A Low-Voltage Data Signaling (LVDS) serial link is used for the data transfer between the two on-detector parts (15 m apart) and G-Link (Hewlett-Packard 1.4 Gbaud high speed data link) with optical transmission (90 m) is used from one of the on-detector parts to the off-detector part. These components will be exposed to a radiation of approximately 200 Gy (including safety factors) for ten years corresponding to a total ionizing dose (TID) and a hadron fluence of 2/spl times/10/sup 10/ hadrons/cm/sup 2/. We have investigated systematically the radiation susceptibility to both the total ionizing dose and the single event effects for ASIC, FPGA, and Commercial Off The Shelf (COTS) serializer and deserializer chipsets for two types of LVDS serial link and one G-Link type. In this documentation we report the result of the irradiation tests for these devices and discuss their validity in the ATLAS system.

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>